Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1998-09-01
2001-08-21
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S262000
Reexamination Certificate
active
06278143
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to a semiconductor device and particularly, to a complex-type bipolar transistor device comprising a bipolar transistor and a junction-type field effect transistor and its manufacturing method.
2. Background of the Invention
As shown in
FIG. 1
, a fact that a complex structure high breakdown bipolar transistor is constituted by cascode-connecting a high breakdown voltage junction-type field effect transistor J-FET to a bipolar transistor TR is disclosed, for example, in Japanese laid-open patent publication No. 53-67368.
According to this structure, when a high voltage is applied to a collector side terminal C of the bipolar transistor TR, a depletion layer spreads from a gate junction of the junction-type field effect transistor J-FET giving rise to a pinch-off and as a result, it is interrupted that a high voltage is applied to a collector region of the bipolar transistor TR. That is, as for a collector to emitter voltage Vce of the bipolar transistor TR, only a voltage less than a pinch-off voltage Vp of the junction-type field effect transistor J-FET is applied, thereby making it possible to implement high breakdown voltage in a low withstand voltage bipolar transistor.
In the case of this structure, however, a maximum handling electric current in the bipolar transistor TR is limited to less than a saturation current I dss of the junction-type field effect transistor J-FET. Consequently, when it is tried to increase the saturation current I dss of the junction-type field effect transistor J-FET, there arises a need to make its gate width (channel width) larger, thereby giving rise to an inconvenience that an area occupied by the junction-type field effect transistor J-FET becomes larger.
On the other hand, a complex-type high breakdown voltage bipolar transistor capable of handling at least a large electric current below the saturation current I dss of the junction-type field effect transistor J-FET is proposed by, for example, Japanese laid-open patent publication No. 54-89581.
According to this proposal, for example, as shown in
FIG. 2
, a collector of an npn type bipolar transistor TR is connected to a source of a junction-type field effect transistor J-FET and at the same time, a base of the bipolar transistor TR is connected to a gate G of the J-FET. In this case, when a high voltage is applied to the collector side terminal C, the junction-type field effect transistor J-FET is put into the pinch-off so that only a voltage less than a pinch-off voltage vp of the J-FET is applied to the bipolar transistor TR, with the result that the high breakdown voltage is implemented in the low operating bipolar transistor TR. In this case, when the bipolar transistor TR is in a state of saturation, the gate of the J-FET is biased in a forward direction, thereby making it possible to handle a large electric current exceeding the saturation electric I dss current of the J-FET.
In these structures, in order to implement the high breakdown voltage of the low operating voltage transistor in the bipolar transistor TR, it is necessary to reduce the pinch-off voltage Vp in the junction-type field effect transistor J-FET.
Also, in the case of these structures, as the part between the source and the drain of junction-type field effect transistor FET is serially connected to the collector of the bipolar transistor TR, there is a demand that the ON resistance of the J-FET is selected as low as possible in order to obtain a high speed responsiveness and a-high frequency characteristic.
However, in order to implement the reduction of the ON resistance in the J-FET and the improvement of the saturation current Idss in the J-FET, it is necessary to increase the impurity concentration in a channel portion. When the concentration in the channel portion is increased, it entails an increase in the pinch-off voltage Vp, thereby making the reduction of the pinch-off voltage Vp incompatible with the reduction of the ON resistance and the improvement of the Idss. Also, in order to increase the Idss and implement the reduction of the ON resistance without increasing the pinch-off voltage Vp, it is conceivable that a gate width is made larger, but in this case, the area occupied by the J-FET increases, thereby impeding high density of a device and implementation of a lesser area.
SUMMARY OF THE INVENTION
The present invention is, as mentioned above, in a semiconductor device by a complex-type bipolar transistor device wherein a junction-type field effect transistor is connected to a bipolar transistor, to provide a semiconductor device and its manufacturing method which makes it possible to ensure a good and stable characteristic of the bipolar transistor without incurring an area to become larger in the junction-type field effect transistor J-FET.
The present invention is arranged, in a semiconductor device comprising a bipolar transistor and a junction-type field effect transistor, in which a collector of the bipolar transistor and a source of the junction-type field effect transistor are connected, such that a gate contact conductive layer which is put in ohmic-contact with a gate region of the junction-type field effect transistor and a drain contact conducive layer which is put in contact with a drain region are formed of conductive layers which are formed of conductive layers as respectively different layers made of a same conductive material or mutually different conductive materials, and an arrangement surface at an edge portion on a drain side of the gate contact conductive layer is formed by being positioned below an arrangement surface at an edge portion on a gate side of the drain contact conductive layer.
Also, the present invention is, in a method for manufacturing a semiconductor device comprising a bipolar transistor and a junction-type field effect transistor, in which the collector of the bipolar transistor and the source of the junction-type field effect transistor are connected, to obtain a target semiconductor device in a way that by carrying out a process for forming a gate contact conductive layer in the junction-type field effect transistor, a process for forming an inter-layer insulating layer on the gate contact conductive layer and thereafter, a process for forming a drain contact conductive layer which forms the drain contact conductive layer of the junction-type field effect transistor, the arrangement surface at the edge portion on the drain side of the gate contact conductive layer is so formed as to be positioned above the arrangement surface at the edge portion on the gate side of the drain contact conductive layer.
In the meantime, the arrangement surface at the edge portion of the contact conductive layer in this specification is, in a case where the contact conductive layer is of a multi-layer structure, for example, lamination-layer structured by a contact conductive layer consisting of a semiconductor layer, a contact conductive layer consisting of a metal layer and the like, to indicate the arrangement surface at the edge portion of the conductive layer in a low layer.
Meanwhile, according to the above-mentioned arrangement of the present invention, as the arrangement surface at the edge portion on the drain side of the gate contact conductive layer in the junction-type field effect transistor is made to be a different surface from the arrangement surface at the edge portion on the gate side of the drain contact conductive layer, both the conductive layers can be arranged to be close enough or overlapping one another, while retaining the areas of both the conductive layers in a necessary and sufficient state and further, because the gate portion and the drain electrode contact portion can resultantly be arranged adequately close, high density, reduction of the ON resistance as well as improvement of Idss are implemented.
Also, the arrangement surface at the edge portion on the drain side of the gate contact conductive layer is made to be different from the arrangement surface at the edge portion on
Jackson, Jr. Jerome
Sonnenschein Nath & Rosenthal
Sony Corporation
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