Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
1999-03-29
2001-10-16
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S734000, C438S401000, C438S640000, C438S975000
Reexamination Certificate
active
06304001
ABSTRACT:
BACKGROUND OF THE INVENTION
1 Field of the Invention
The present invention relates to a semiconductor device with an alignment mark and a manufacturing method thereof, and particularly to a semiconductor device with an alignment mark and a manufacturing method thereof facilitating alignment mark detection and improving alignment accuracy.
2 Description of the Background Art
FIG. 21
is a section of a semiconductor device having a multilayer interconnection structure. In this semiconductor device, a gate interconnection
3
is formed on a semiconductor substrate
1
with an insulation film posed therebetween. Gate interconnection
3
is placed between source/drain regions
4
formed in semiconductor substrate
1
.
A first metal interconnection layer
6
, of aluminum or the like, is formed on gate interconnection
3
with an interlayer insulation film
5
posed therebetween. First metal interconnection layer
6
is electrically connected with source/drain region
4
via a contact hole
5
a.
A second metal interconnection layer
8
, of aluminum or the like, is formed on first metal interconnection layer
6
with an interlayer insulation film
7
posed therebetween. Second metal interconnection layer
8
is electrically connected with first metal interconnection layer
6
via a contact hole
7
a
, and covered with a protective film
11
.
In this structure, precise interconnections between first metal interconnection layer
6
and gate interconnection
3
and second metal interconnection layer
8
and first metal interconnection layer
6
are necessary. Therefore, the precise formation of a resist film, which is used for the patterning of first metal interconnection layer
6
and second metal interconnection layer
8
, is required.
Conventionally an alignment mark is used for the positioning of the resist film for the patterning of first metal interconnection layer
6
and second interconnection layer
8
. As an example, an alignment mark formed in interlayer insulation film
5
for the positioning of the resist film used for the patterning of first metal interconnection layer
6
will be described referring to
FIGS. 22 and 23
.
With reference to
FIGS. 22 and 23
, an alignment mark
4
formed in interlayer insulation film
5
is formed as a recess portion being rectangular in plan and having two sets of opposing sidewalls
4
a
,
4
b
and
4
c
,
4
d
. In recent years, for the improvement of a coverage, first metal interconnection layer
6
has been deposited on alignment mark
4
by an interconnection process using a high temperature aluminum sputtering technique.
The high temperature sputtering technique is different from a normal sputtering technique in that a heat treatment at 300° C.-600° C. is performed during or after the deposition of a film.
As a result, an aluminum grain
6
A grows large as shown in
FIGS. 22 and 23
and an aluminum material flows in the recess portion, whereby a gentle-sloped side surface is formed in a region enclosed and designated by A in FIG.
23
.
At the detection of a resist film side alignment mark used for the patterning of first metal interconnection layer
6
, signals P
1
and P
3
corresponding to side surfaces
9
a
and
9
b
of resist film side alignment mark
9
can easily be located because of high strength and distinct peaks of these signals as can be seen from
FIG. 24
showing detection signal strength measured at a section taken along a line X
1
-X
1
′ of FIG.
22
.
On the other hand, signals P
2
and P
4
corresponding to side surfaces
6
a
and
6
b
of first metal interconnection layer
6
, which are deposited on sidewalls
4
a
and
4
b
of alignment mark
4
in the insulation layer, cannot be located accurately because of their low strength and indistinct peaks. Therefore, accurate measurements of a distance L
1
between signal P
1
and signal P
2
and a distance L
2
between signal P
3
and signal P
4
cannot be obtained.
FIG. 25
shows detection signal strength measured at a section taken along a line X
2
-X
2
′ of FIG.
22
and
FIG. 26
shows detection signal strength measured at a section taken along a line X
3
-X
3
′ of FIG.
22
. As can be seen from the comparison of these drawings, a largely grown aluminum grain
6
A causes the fluctuation of the detected locations of signals P
2
and P
4
corresponding to side surfaces
6
a
and
6
b
of first metal interconnection layer
6
deposited on sidewalls
4
a
and
4
b
of alignment mark
4
, depending on the measurement points.
Above described problems hinder the easy and accurate detection of the locations of signals P
2
and P
4
corresponding to side surfaces
6
a
and
6
b
of first metal interconnection layer
6
deposited on sidewalls
4
a
and
4
b
of alignment mark
4
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device with an alignment mark and a method of manufacturing the same allowing the easy and accurate detection of the location of an interconnection layer deposited on a sidewall of the alignment mark.
In the semiconductor device with the alignment mark in accordance with the present invention, the alignment mark, which is formed on an insulation layer in order to detect the location of interconnection layer formed on the insulation layer, is a recess portion being approximately rectangular in plan and having two sets of opposing sidewalls, wherein the recess portion includes a film growth control region for forming on a surface opposite to the sidewalls, a side surface of the interconnection layer, which is formed in the recess portion, approximately parallel with the sidewalls at the deposition of the interconnection layer.
In one specific aspect of the semiconductor device with the alignment mark, the film growth control region includes a convex portion arranged in the recess portion such that it opposes to the sidewall.
With the alignment mark having the film growth control region with above mentioned structure, when the interconnection layer is formed by the high temperature sputtering on the insulation layer having the alignment mark, a surface of the sidewall opposite to the convex portion and a surface of the convex portion opposite to the sidewall each serve as a block with respect to an angle of incidence of grains sputtered for forming the interconnection layer.
Thus, as a few grains sputtered for the formation of the interconnection layer enter and are deposited on the surface of sidewall opposite to the convex portion and the surface of convex portion opposite to the sidewall, the deposition of interconnection layer on these portions are small.
As a result, the grain growth of interconnection layer and the flow of interconnection layer material in this area are suppressed. Thus a side surface of the interconnection layer approximately parallel with the sidewall is formed both on the surface of the sidewall opposite to the convex portion and on the surface of the convex portion opposite to the sidewall. The formation of these two side surfaces of interconnection layer allows easy and accurate detection of the location of interconnection layer deposited on the alignment mark.
In the semiconductor device with the alignment mark, preferably, the convex portion has a sharp ridge portion at its upper end and the sidewall has a taper parting from the convex portion as it goes upward at an upper end region facing the convex portion.
By this structure, the grain growth of interconnection layer and the flow of interconnection layer material are suppressed also at the upper end of the convex portion. Therefore, the easy and accurate detection of the location of interconnection layer deposited on the alignment mark is allowed by the upper end portion of the convex portion.
In another specific aspect of the semiconductor device with the alignment mark, the insulation layer is formed on two lower interconnection layers arranged parallel to each other in a direction not parallel with a direction of interconnection layer's extension, the recess portion is formed in the insulation layer placed
Hagi Kimio
Kimoto Mitsuo
Sekiguchi Noboru
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Quach T. N.
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