Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-03-07
2001-05-08
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S758000
Reexamination Certificate
active
06229195
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device with air gaps between interconnections and a method of forming the same.
A conventional method of forming a semiconductor device will be described with reference to
FIGS. 1A through 1D
.
With reference to
FIG. 1A
, an inter-layer insulator
2
is formed on a bottom level interconnection
1
. A first photo-resist film
12
is selectively formed over the inter-layer insulator
2
. The inter-layer insulator
2
is then subjected to a dry etching by use of the first photo-resist film
12
as a mask to form trench grooves
7
which provide spaces for later formation process for forming second level interconnections, so that the trench grooves
7
have bottoms which lie over an interface between the first level interconnection
1
and the inter-layer insulator
2
.
With reference to
FIG. 1B
, the first photo-resist film
12
is removed before a second photo-resist film
13
is selectively formed on the inter-layer insulator
2
and within the trench grooves
7
except for a part of the trench groove
7
. The inter-layer insulator
2
is further subjected to a further dry etching by use of the second photo-resist film
13
as a mask to form a through hole
8
which reaches the interface between the first level interconnection
1
and the inter-layer insulator
2
so that a part of the first level interconnection
1
is shown through the through hole
8
.
With reference to
FIG. 1C
, the second photo-resist film
13
is removed before a metal film
10
of AlCu is entirely deposited by a high temperature sputtering method so that the metal film
10
extends over the inter-layer insulator
2
as well as within the trench grooves
7
and within the through hole
8
.
With reference to
FIG. 1D
, the metal film
11
is then subjected to a chemical and mechanical polishing for selective removal of the metal film
11
, so that the metal film
10
remain only within the trench grooves
7
and the through hole
8
, whereby second level interconnections
11
are formed in the trench grooves
7
and a contact layer is formed in the through hole
8
. As a result, the second level interconnections
11
are electrically connected through the contact layer to the first level interconnection
1
.
The above fabrication processes are so called as Dual-Damascene Process which is effective for scaling down the semiconductor device and realizing quarter-micron design rule without raising a problem with a high cost of manufacturing the semiconductor device due to complicated fabrication processes.
The above Dual-Damascene Process, however, has the following problems. In order to reduce a capacitance between the same level interconnections, it is effective to form an air gap between the same level interconnections. The formation of the air gap between the same level interconnections requires a photo-resist technique. In the conventional fabrication processes, an inter-layer insulator has been formed before the inter-layer insulator is etched to form regions in which interconnections will be formed An adjustment to conditions for forming the inter-layer insulator may prevent formation of the air gap. The air gap is formed as follows. A photo-resist film is formed over the inter-layer insulator. The photo-resist film is then patterned by a photolithography to form a mask. The inter-layer insulator is then subjected to a dry etching by use of the photo-resist film as a mask to form openings for formation of the air gap. The photo-resist film is removed before an insulation film is then formed over the inter-layer insulator and within the openings, thereby to form an air gap. The above processes are additional to the conventional fabrication processes.
In the above circumstances, it had been required to develop a novel method of forming air gaps between the same level interconnections without addition of the photo-resist process so that the air gaps reduce the parasitic capacitance between the interconnections. The reduction in the parasitic capacitance between the interconnections improves high speed performance of the semiconductor device.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel air gap between the same level interconnections free from the above problems.
It is a further object of the present invention to provide a novel air gap between the same level interconnections which may be formed without addition of a photo-resist process.
It is a still further object of the present invention to provide a novel interconnection structure which has a reduced parasitic capacitance.
It is yet a further object of the present invention to provide a novel semiconductor device having an interconnection structure with air gaps.
It is furthermore object of the present invention to provide a novel method of forming an air gap between the same level interconnections free from the above problems.
It is moreover object of the present invention to provide a novel method of forming an air gap between the same level interconnections without addition of a photo-resist process.
It is still more object of the present invention to provide a novel method of forming an interconnection structure which has a reduced parasitic capacitance.
It is yet more object of the present invention to provide a novel method of forming a semiconductor device having an interconnection structure with air gaps at a low cost.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
The present invention provides a semiconductor device comprising an inter-layer insulator, first level interconnections extending on a bottom of the inter-layer insulator, second level interconnections extending on a top of the inter-layer insulator, at least a through hole formed in the inter-layer insulator so that the through hole provides a connection between the first level and second level interconnections, and a plurality of air gaps formed in the inter-layer insulator so that the air gaps are disposed between adjacent two of the second level interconnections, wherein the air gaps have substantially the same shape in plan view as the through hole.
The present invention also provides a method of forming a semiconductor device. The method comprises the following steps. At least a first opening and at least a second opening are concurrently formed in a dielectric layer which has a bottom portion having first level interconnections so that the first and second openings have a bottom level which lies over the first level interconnections. A dielectric film is deposited over the dielectric layer to form an inter-layer insulator so that top portions of the first and second openings are sealed with the dielectric film so as to form at least a first hollow portion and at least a second hollow portion serving as an air gap. A plurality of grooves are selectively formed in an upper portion of the inter-layer insulator so that at least one of the grooves extend on a top portion of the first hollow portion whereby the top portion of the first hollow portion reaches a bottom of the groove, and also so that the second hollow portion is disposed between adjacent two of the grooves. A bottom of the first hollow portion is selectively etched so that the bottom of the first hollow portion reaches a top of one of the first level interconnections so as to form a through hole which connects the at least one of the grooves to the one of the first level interconnections. Second level interconnections are formed in the grooves and a contact layer is formed in the through hole.
REFERENCES:
patent: 5585662 (1996-12-01), Ogawa
patent: 5861674 (1999-01-01), Ishikawa
patent: 6025260 (2000-02-01), Lien et al.
“Damascene”, pp. 179-184, Semiconductor World, Dec. 1995 and (Abridged English translation).
NEC Corporation
Wojciechowicz Edward
Young & Thompson
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