Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-05-13
2001-04-10
Carroll, J. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S632000, C257S668000, C257S673000
Reexamination Certificate
active
06215169
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device in which a tape that is adhered to the surface of a chip, the adhesive layer of this tape, for example a tape of LOC structure (lead on chip tape), being disposed so as not to overlap with an opening in a cover of the semiconductor element surface.
2. Description of the Related Art
A tape of LOC structure (lead on chip tape) usually has a three-layer structure, with adhesive on the front and back of a base material. The adhesive used is often a thermally cured adhesive or a thermally plastic adhesive. Such an adhesive contains a large amount of ionic impurities. As is the same with the LOC tape, CSP (chip scale package) tape that has an wiring layer is adhered to the front surface of the chip, using an adhesive or the like that has insulating properties, the semiconductor element bonding pads and tape interconnect layer being connected by means of wire bonding that uses gold wires, thereby serving to make connection from the interconnect layer to the outside, for example, by ball terminals.
With reference to the prior art references, we will briefly describe them as follows
In the Japanese Unexamined Patent Publication No.08-031879, the semiconductor device includes a semiconductor chip having a surface arranged with inner wiring terminals, a wiring layer fixed through an adhesive layer to the surface of the semiconductor chip, and outer wiring terminals arranged on the periphery of the semiconductor chip. The surface wiring layer has one end part connected electrically with the inner wiring terminals and the other end part connected electrically with the outer wiring terminals. For example, a copper foil TAB lead of 35 &mgr;m thick has one end thermo-compressed to the inner wiring terminal through a gold bump and the other end extending outward from the circumference of the semiconductor chip and thermo-compressed to the lead frame. The TAB lead is bonded to the surface of the semiconductor chip through the adhesive layer.
The Japanese Unexamined Patent Publication No.08-162598 recites a semiconductor device having a structure formed by bonding the inner lead of the lead frame on a semiconductor chip or a heat-radiating plate via an adhesive tape to ensure sufficient bonding between an inner lead of a lead frame and a bonding wire to make the bonding suitable for high mounting density. A recess is formed near a bond part of an upper surface of each inner lead of a lead frame to be bonded via an adhesive tape on a semiconductor chip, which bond part is to be bonded to a bonding wire. Upon bonding, the tip side of the inner lead is made not to sink in the adhesive tape by the recess so that the contact area between the bonding wire and the inner lead is not decreased.
The Japanese Unexamined Patent Publication No.09-260535 provides a ball grid array type of semiconductor package, and this is composed of a semiconductor chip where a bonding pad is made, an elastomer which is bonded to the semiconductor chip , a flexible wiring board which is bonded to the elastomer and in which wiring whose lead is connected to the bonding pad of the semiconductor pad is made, a solder resist which is made on the main surface of the flexible wiring board, and a bump which is connected to the bump land of the wiring .This is the so-called surface wiring structure where the elastomer is bonded to the semi-conductor chip side of the tape of the flexible wiring board, and besides the solder resist is made on the solder bump side of the wiring.
The Japanese Unexamined Patent Publication No.10-032287 provides a resin-sealed semiconductor device which is equipped with a semiconductor element, leads connected to the circuit-formed surface of the element and arranged above it, gold wires which connect the semiconductor device with the leads, and an insulating tape provided between a part of the leads and the semiconductor element to fix the leads to the semiconductor element. A frame-shaped dam bar nearly equal in external shape to the circuit-formed surface is fixed onto the circuit-formed surface through the intermediary of the adhesive tape so as not to come into contact with the leads. Molding resin is filled inside the dam bar to seal up the circuit-formed surface without covering the upside of the leads, and the surface except the circuit-formed surface is kept exposed.
FIG.
5
(
a
) is a cross-sectional view of a prior art semiconductor device, FIG.
5
(
b
) is a plan view thereof, which shows the condition in which the lead frame has been removed from the structure shown in FIG.
5
(
a
), FIG.
5
(
c
) is a plan view showing the condition in which the tape is removed, and FIG.
5
(
d
) is an enlarged cross-sectional view along the line D—D that is shown in FIG.
5
(
b
).
The LOC tape
3
exists on the active surface of the semiconductor element
2
, that is, on the top of the so-called circuit surface
2
a
, the element
2
being fixed to the lower surface thereof and an internal lead being fixed to the upper surface thereof. The internal lead
6
and the bonding pad
9
of the semiconductor element
2
are electrically connected by means of a bonding wire (made of gold)
5
. Therefore, the LOC tape
3
is of a shape that avoids the bonding pad
9
. However, the LOC tape
3
is adhered so as to overlap the cover aperture part (fuse and the like)
10
a
of the outermost surface of the semiconductor element other than the bonding pad location.
The LOC tape
3
usually has a three-layer structure, with adhesive on the front and back of a base material. The adhesive used is often a thermally cured adhesive or a thermally plastic adhesive. Such an adhesive contains a large amount of ionic impurities.
As described above, if an LOC tape is shaped so that the LOC tape does not overlap with the cover aperture of the semiconductor element, there is no corrosion of fine interconnects caused by impurities in the LOC tape.
The above is also true with regard to CSPs (chip scale packages). In the case of a CSP, a tape that has an wiring layer is adhered to the front surface of the chip, using an adhesive or the like that has insulating properties, the semiconductor element bonding pads and tape interconnect layer being connected by means of wire bonding that uses, for example, gold wires, thereby serving to make connection from the interconnect layer to the outside, for example, by ball terminals.
In the same manner as noted for an LOC tape, because the adhesive of this tape that has an interconnect layer for use in an CSP is adhered to the cover aperture part of the uppermost surface of the semiconductor element other than the bonding pad, impurities in the tape contaminate and cause broken connections in such thin interconnect parts as the fuses at the cover aperture at the uppermost surface of the semiconductor element.
Accordingly, it is an object of the present invention to provide a semiconductor device wherein the adhesive layer of an LOC (lead on chip) tape that is adhered to the chip surface is disposed so that it does not overlap onto the cover aperture of the surface of the semiconductor element.
SUMMARY OF THE INVENTION
In order to achieve the above-noted object, the present invention adopts the following basic technical constitution.
A semiconductor device according to the present invention has a tape that is adhered to the surface of the chip so that it is disposed in a manner that it does not overlap with the cover aperture of the semiconductor surface.
In the present invention, it is desirable that the above-noted tape be at least 0.1 mm distant from the cover aperture of the semiconductor element surface, and further that, in the case in which there are two or more covers that overlap, the tape be at least 0.1 mm distant from the cover on the uppermost surface of the semiconductor element.
It is also desirable that the above-noted aperture includes a fuse aperture, or that it includes a bonding pad part and fuse aperture.
REFERENCES:
patent: 5932485 (1999-08-01), Schofield
patent: 60
Carroll J.
McGinn & Gibb PLLC
NEC Corporation
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