Semiconductor device with a staggered pad arrangement

Details Semiconductor device with a staggered pad arrangement Semiconductor device with a staggered pad arrangement

2002-11-12

2004-04-13

Le, Dung (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S673000, C257S737000

Reexamination Certificate

active

06720636

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a pad and a pad-control portion that controls the input/output signals of the pad.
2. Description of the Prior Art
FIG. 9
is a layout diagram showing a conventional semiconductor device that operates with two power supplies (internal and external power supplies). Referring to the figure, reference numeral
1
a
,
1
b
denote respectively pads including an internal row pad
6
and an external row pad
7
; and
2
denotes a pad-control portion which is electrically connected to the pad
1
a
,
1
b
and which controls an input signal from the pad
1
a
,
1
b
and an output signal to the pad
1
a
,
1
b
. In the pad-control portion
2
, reference numeral
3
denotes a protection portion that is composed of capacitance, for instance, and electrically protects elements within the semiconductor chip;
4
denotes a level shifter portion that converts the input and output signals between the internal power supply and the external power supply; and
5
denotes a logic portion that is composed of logical circuits or the like, and logically converts the input and output signals.
Reference numeral
6
denotes an internal row pad that has a short length between the pad
1
a
and the pad-control portion
2
, and
7
denotes an external row pad that has a long length between the pad
1
b
and the pad-control portion
2
.
Reference numeral
8
denotes a distance between the pads
1
a
,
1
b
of the external row pads
7
which are adjacent to each other.
Reference symbol VDD represents an internal power supply wiring; VSS represents an internal ground wiring; VDDX represents an external power supply wiring; and VSSX represents an external ground wiring. These wirings are used for supplying power to the pad-control portions
2
.
The operation will now be described as below.
Referring to
FIG. 9
, the pads
1
a
,
1
b
each are provided with the pad-control portion
2
. The pad-control portion
2
level-shifts or controls the input/output signals of the pad
1
a
,
1
b
by use of two power supplies from the internal power supply wiring VDD and the internal ground wiring VSS; and the external power supply wiring VDDX and the external ground wiring VSSX.
There is a restraint in minimum size of the pads
1
a
,
1
b
because the pads
1
a
,
1
b
each are bonded with a wire. Moreover, there is also a restraint in minimum length of the spacing between the adjacent pads
1
a
,
1
b
because the deterioration of the electrical properties of the input/output signals must be prevented.
By the way, a smaller area of a semiconductor chip has recently been required, and on the other hand, multiple pins on the chip have been developed with an increase in the functionality of semiconductor devices. For this reason, in
FIG. 9
, the short and the long distances between the pads
1
a
,
1
b
and the pad-control portion
2
are alternately used, and the pads
1
a
,
1
b
are disposed in a staggered arrangement. Thereby, the area to be occupied by the pads
1
a
,
1
b
and the pad-control portions
2
can be reduced to meet the demand of increasing pins on the chip. The lay-out of such pads
1
a
,
1
b
is referred to as a staggered pad herein. The portion consisting of a pad
1
a
and a pad-control portion
2
, having a shorter distance between the pad
1
a
and the pad-control portion
2
is referred to as an internal row pad
6
, and the portion composed of a pad
1
b
and a pad-control portion
2
, having a longer distance between the pad
1
b
and the pad-control portions
2
is referred to as an external row pad
7
.
The conventional semiconductor device is arranged as mentioned above. Thus, the area to be occupied by the pads
1
a
,
1
b
and the pad-control portions
2
is reduced to meet the demand of increasing pins by means of disposing the pads in a staggered arrangement. However, in such an arrangement, the distance
8
between the pads
1
a
,
1
b
adjacent to each other of the external row pads
7
is longer, as shown in FIG.
9
.
As described above, there has been a drawback that a smaller area of the semiconductor chip is avoided since the area not occupied by elements thus remains on the semiconductor chip.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above-mentioned drawback. An object of the present invention is to provide a semiconductor device which reduces the layout area of pads and pad-control portions to thereby perform a smaller area of a semiconductor chip.
According to one aspect of the present invention, there is provided a semiconductor device in which a pad and a pad-control portion within an internal row pad are disposed in a relationship of reversed arrangement with the pad and the pad-control portion within an external row pad; the pads and the pad-control portions of the internal row pad and of the external row pad are disposed in the same direction as the bonding direction; and a plurality of the internal row pads and a plurality of the external row pads each are alternately disposed adjacent perpendicularly to the bonding direction.
According to another aspect of the present invention, there is provided a semiconductor device in which a pad and a pad-control portion within an internal row pad are disposed in a relationship of reversed arrangement with the pad and the pad-control portion within an external row pad; the pads and the pad-control portions of the internal row pad and of the external row pad are disposed perpendicularly to the bonding direction; and a plurality of the internal row pads and the external row pads forming a pair in the bonding direction are disposed perpendicularly to the bonding direction.
According to still another aspect of the present invention, the internal row pads and external row pads are disposed in a staggered arrangement closer to the chip outside than the pad-control portion, and at least one corner of the rectangular pattern is rounded off in the pattern shape of the pad.
As mentioned above, according to the present invention, the area occupied by the pad and the pad-control portion can be reduced in the bonding direction, thereby effecting a smaller area of the semiconductor chip.


REFERENCES:
patent: 6-275794 (1994-09-01), None
patent: 7-74456 (1995-03-01), None
patent: 11-145328 (1999-05-01), None
patent: 2000-243878 (2000-09-01), None

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