Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-02-25
2003-09-23
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S371000, C257S370000, C257S373000, C257S378000, C257S512000, C438S309000, C438S313000, C438S318000, C438S207000, C438S213000, C438S208000
Reexamination Certificate
active
06624497
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Related to a corresponding application entitled Reduced Mask Count Buried Layer Process
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices and its manufacturing method, and, more specifically, to the formation of buried layers in such devices.
2. Description of Related Art
It is well known in semiconductor processing that the minimization of the number of masking operations in fabricating a semiconductor device is a constant goal. Thus processes which can eliminate a masking operation are highly desirable in the semiconductor processing art.
Fabrication of complementary vertical bipolar devices for analog signal processing on a single integrated circuit with N type and P type buried layers are known in the art. For example, Rupit Patel et al, “a 30 V Complementary Bipolar Technology on SOI for High Speed Precision Analog Circuits,” IEEE BCTM, pp. 48-50, 1997, and M. C. Wilson et al, “Process HJ: A 30 GHz NPN and 20 GHz PNP Complementary Bipolar Process for High Linearity RF Circuits,” IEEE BCTM, pp. 164-167, 1998, describe examples of these types of circuits. In both publications the circuits taught use both N type and P type buried layers which are formed using separate mask and implant steps to form each buried layer. This requires two masks and two implants to form the two buried layers.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a semiconductor processing method which provides a non selective N buried layer without requiring a masking operation, together with a selective P type buried layer which is formed using a mask. It is also an object of this invention to provide a semiconductor device with a non selective N type buried layer and a selective P type buried layer.
According to the invention, there is provided a semiconductor process wherein a non selective N type buried layer and a selective P type buried layer are formed on a an semiconductor device, the dopant used as the N type buried layer dopant having a lower diffusion coefficient than the dopant used as the P type buried layer dopant.
According to the invention, there is further provided a semiconductor device having a non selective N type buried layer and a selective P type buried layer formed on a semiconductor device, the N type majority dopant present in the N type buried layer dopant having a lower diffusion coefficient than the P type majority dopant present in the P type buried layer dopant.
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Rupit Patel, et al., A 30V Complementary Bipoar Technology on SOI for High Speed Precision Analog Circuits, 1997 IEEE BCTM, pp. 48-50.
MC Wilson, et al., Process HJ: A 30 GHz NPN and 20 GHz PNP Complementary Bipolar Process for High Linearity RF Circuits, 1998 IEEE BCTM, pp. 164-167.
Im Junghwa
Intersil Americas Inc
Robinson Richard K.
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