Semiconductor device with a nonvolatile semiconductor memory...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185090, C365S185110

Reexamination Certificate

active

11008960

ABSTRACT:
Only by replacing a conventional fuse element used for a redundant repair of a memory with a CMOS device, since physical processing is not required, there is an advantage on a circuit area in which the upper interconnection can be utilized. However, on a design of a semiconductor device, since the CMOS device requires application of a high voltage for rewriting, there is a problem of being subjected constraint of an arrangement of an interconnection or a semiconductor circuit. For that reason, by arranging the nonvolatile semiconductor memory circuit provided with the nonvolatile memory device which is constituted of a CMOS device between the IO blocks arranged at the periphery of the chip, physical processing due to replacing the conventional fuse element with the CMOS device will not be needed, so that while keeping an advantage on a circuit area that the upper interconnection can be utilized, the problem of the arrangement in consideration of high voltage application can be resolved.

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T. Takahashi, et al.; “A Multi-Gigabit DRAM Technology with 6F2Open-Bit-Line Cell Distributed Over-Driven Sensing and Stacked-Flash Fuse,” ISSCC 2001/Session 24/DRAM/24.2, 2001 IEEE International Solid-State Circuits Conference, pp. 380-468.

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