Semiconductor device with a charge pumping circuit

Details Semiconductor device with a charge pumping circuit Semiconductor device with a charge pumping circuit

2000-03-13

2002-04-16

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000, C365S189090, C363S060000

Reexamination Certificate

active

06373325

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-073491, filed Mar. 18, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a charge-pumping circuit which produces a boosted voltage. More particularly, this invention pertains to a charge-pumping circuit which is demanded of low power consumption while a device in which the charge-pumping circuit is installed is stopping operation or is in a standby mode.
The microfabrication technology and schemes to reduction in the source voltage have improved the performances of semiconductor devices. Some of the semiconductor devices, such as memories which cannot set the voltage to be applied to memory cells or the like equal to an external voltage, incorporate a voltage boosting circuit or a charge-pumping circuit.
The electric potential boosted inside a chip by the charge-pumping circuit is maintained even when the chip is stopped (inactive or standby mode). This is to assure the chip performances, such as the access time, immediately after the transition from the standby state to the active state.
To hold the boosted potential even in the standby state, the charge-pumping circuit is designed to always monitor the boosted voltage level and automatically restart the charge-pumping operation if the inner potential drops due to leakage or the like in transistors. To achieve this function, the current dissipation of a device which carries out inner voltage boosting does not become zero even in standby mode. (This current will hereinafter be called “standby current”.)
Recently, it has become typical to incorporate devices which implement inner voltage boosting into portable devices. This naturally makes the demand of reducing the standby current severer. This is because portable devices basically operate on the battery voltage so that even slight current flowing in such a portable device directly affects the performance of the device, such as making the standby time of the device shorter.
Accordingly, the allowed standby current of the charge-pumping circuits becomes smaller than the conventional standby current. The operation of the conventional charge-pumping circuit will now be described specifically from the viewpoint of reducing the standby current.
FIG. 1
is a diagram showing the structure of a typical conventional charge-pumping circuit. The main portion of the conventional charge-pumping circuit shown in
FIG. 1
comprises transistors Qi (i: natural number) which has gate-drain common connection and capacitors Ci whose one electrodes are connected to the drains of the respective transistors Qi.
Multiple stages of circuits each comprising the transistor Qi and capacitor Ci are connected in series (i is 1 to 4 in this example) and the capacitor Ci of each stage is driven alternately to an “H” (High) level and an “L” (Low) level, thereby transferring charges.
Reference symbol “Qin” denotes an input transistor. The input end of the current path formed by the transistors Qi and the capacitors Ci is connected to an external voltage VDDO. A boosted output voltage VDDR is output from the source of the transistor Q
4
of the last stage.
A control system for the conventional charge-pumping circuit as illustrated in
FIG. 1
is constructed as follows.
An enable signal ENABLE is supplied to one input terminals of NAND gates NAND
1
and NAND
2
. The output of the NAND gate NAND
1
is supplied to the gate of the transistor Qin via an inverter IV
1
.
The output signal, OSC, of an unillustrated oscillator is supplied to the other input terminal of the NAND gate NAND
2
. The output of the NAND gate NAND
2
is separated into two paths to alternately drive the capacitors Ci. Specifically, the output of the NAND gate NAND
2
is supplied to the other electrodes of the capacitors C
1
and C
3
via inverters IV
2
, IV
3
and IV
4
in one path, and is supplied to the other input terminal of the NAND gate NAND
1
and the other electrodes of the capacitors C
2
and C
4
via the inverter IV
2
and an inverter IV
5
in the other path.
This charge-pumping circuit is activated when the signal ENABLE becomes an “H” level. When the signal ENABLE becomes the “H” level, the output of the NAND gate NAND
2
transfers the output signal OSC (“H”/“L” level) of the oscillator. The output of the NAND gate NAND
1
transfers the output of the inverter IV
5
via the inverter IV
1
, so that a timing signal of an “H”/“L” level is supplied to the gate of the transistor Qin.
The individual capacitors Ci which are connected to nodes adjoining with the associated transistor Qi for charge transfer in between are driven to different levels of “H” and “L”. This allows charges to be transferred from one transistor to another so that the boosted output voltage VDDR is acquired from the transistor Q
4
of the last stage.
From the viewpoint of charge transfer, it is desirable that the threshold voltage of the transistors Qi having diode connection be as close to 0V as possible. To meet this requirement, intrinsic transistors (I-type transistors) which are fabricated without making channel ion implantation in the substrate are used for the transistors (Qin and Qi) that constitute a charge-pumping circuit. Because the I-type transistor on the substrate has a low impurity concentration at the channel portion, the threshold voltage of that transistor can be set to approximately 0V.
FIG. 2A
is a circuit diagram depicting individual potential nodes of an I-type transistor having diode connection formed on a substrate.
FIG. 2B
is a diagram illustrating characteristic curves of the drain current ID versus drain voltage VD of the I-type transistor under the conditions shown in FIG.
2
A.
A substrate potential VB is the ground potential (VB=0V). The log scale (the scale on the left-hand side of the graph) will mainly be referred to when the drain voltage VD is lower than the source voltage VS (equal to the gate voltage VG), and the linear scale (the scale on the right-hand side of the graph) will mainly be referred to when the drain voltage VD is higher than the source voltage VS (equal to the gate voltage VG).
FIG. 3A
is a circuit diagram depicting individual potential nodes of another I-type transistor formed on a substrate.
FIG. 3B
is a diagram illustrating characteristic curves of the drain current ID versus gate voltage VG of the I-type transistor under the conditions shown in FIG.
3
A. As indicated by arrows in
FIG. 3B
, the log scale on the left-hand side will be referred to for the upper curves and the linear scale on the right-hand side will be referred to for the lower curves.
FIG. 4A
is a circuit diagram depicting individual potential nodes of an I-type transistor formed on a substrate.
FIG. 4B
is a diagram illustrating characteristic curves of the drain current ID versus gate voltage VG under the conditions shown in FIG.
4
A. As likewise indicated by arrows in
FIG. 4B
, the log scale on the left-hand side will be referred to for the upper curves and the linear scale on the right-hand side will be referred to for the lower curves.
Attention is paid to the states of the individual nodes in the charge-pumping circuit shown in
FIG. 1
when the charge-pumping circuit becomes the standby state from the active state to stop the charge-pumping operation.
In general, in the standby state where the charge-pumping operation is stopped, the signal ENABLE becomes the “L” level, forcibly inhibiting the supply of the output signal OSC of the oscillator. That is, nodes N
1
to N
4
of the capacitors of the individual stages are disabled while having the alternate “H” level and “L” level.
As shown in
FIGS. 2A and 2B
, even when the backward bias is applied to the transistors Qi of the individual stages that have diode connection, the transistors Qi do not go into a cut-off state. With the drain voltage VD being 10V, particularly, a current of about 20 &mgr;A flows when the source voltage VS (VG)

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