Semiconductor device wiring structure

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With extended latchup current level

Reexamination Certificate

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Details

C257S181000, C257S659000, C257S688000

Reexamination Certificate

active

06930333

ABSTRACT:
A semiconductor device wiring structure is provided to reduce the wiring inductance and curtail the generation of interfering electromagnetic waves. A semiconductor chip having an anode electrode and a cathode electrode provided on two oppositely-facing main surfaces is sandwiched between a sheet-shaped anode wiring and a sheet-shaped cathode wiring. The anode and cathode electrodes of the semiconductor chip are connected to the anode and the cathode wirings, respectively, arranged such that the electric currents flowing there-through flow in opposite directions. A conductive substrate having a main surface with a larger width than the cathode wiring is disposed adjacent to the anode wiring. The edges of the cathode wiring protrude beyond the edges of both the anode wiring and the semiconductor chip in all locations and the dimension of the protrusion is at least one half of the distance from the edge of the cathode wiring to the metal substrate.

REFERENCES:
patent: 5463249 (1995-10-01), Shinbo et al.
patent: 5821618 (1998-10-01), Graf et al.
patent: 6060774 (2000-05-01), Terui
patent: 6417527 (2002-07-01), Iwanaga et al.
patent: 6734545 (2004-05-01), Yamamura
patent: 2002/0153532 (2002-10-01), Sonobe et al.
patent: 2003-164040 (2003-06-01), None

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