Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2011-07-19
2011-07-19
Sofocleous, Alexander (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S193000, C365S194000, C365S201000
Reexamination Certificate
active
07983112
ABSTRACT:
A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a transmission circuit which shifts a phase to the set phase to transmit or receive a signal. The transmission circuit has a first phase shifter which shifts a first signal to the set phase, a first bidirectional buffer which loops back the first signal at the test mode time, a second phase shifter which phase-shifts the signal outputted from the first bidirectional buffer, a third phase shifter which phase-shifts a third signal, a second bidirectional buffer which loops back the third signal at the test mode time, a fourth phase shifter which phase-shifts the signal outputted from the second bidirectional buffer, and a FIFO which takes out an output signal of the second phase shifter or the fourth phase shifter.
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Provost et al., “AC IO Loopback Design for high Speed uProcessor IO Test”, ITC International Test Conference, 2004, IEEE, pp. 23-30.
Haraguchi Masaru
Osawa Tokuya
McDermott Will & Emery LLP
Renesas Electronics Corporation
Sofocleous Alexander
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