Semiconductor device which operates at a frequency controlled by

Static information storage and retrieval – Addressing – Sync/clocking

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36523001, G11C 800

Patent

active

054558034

ABSTRACT:
A semiconductor memory device includes a memory cell array, an address part for supplying address signals to the memory cell array, a read/write part for reading data from the memory cell array and writing data into the memory cell array, and an internal clock signal generating circuit for generating an internal clock signal from an external clock signal. The internal clock signal has a cycle with an active-level portion of constant duration independent of a frequency of the external clock signal and is output, as a timing signal, to predetermined structural parts of the address part and/or the read/write part.

REFERENCES:
patent: 4710904 (1987-12-01), Suzuki
patent: 4754163 (1988-06-01), Aue et al.
patent: 4998222 (1991-03-01), Sussman
patent: 5327394 (1994-07-01), Green et al.
patent: 5336939 (1994-08-01), Eitrheim et al.
Horowitz, P. et al., The Art of Electronics, Cambridge University Press, New York, 1987, pp. 351-354.

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