Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – By integrating
Reexamination Certificate
1999-06-24
2003-01-14
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific input to output function
By integrating
C327S334000, C361S091100, C361S091200
Reexamination Certificate
active
06507232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device having an element for adjusting a capacitance value of an input terminal.
2. Description of the Related Art
As for a capacitance value of an input terminal of a memory device such as DRAM or the like, not only the maximum value thereof but also the minimum value thereof is specified as a standard, because of a fact that a memory bus is becoming faster in recent years and other reasons. For this reason, in order to satisfy a lower limit of the capacitance value of the input terminal, it is necessary to connect a capacitance element to the input terminal.
Traditionally, the technique as shown in
FIG. 1
as an element (hereafter, referred to as a capacitance adjusting element) to adjust such a capacitance value of an input terminal is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-138962).
As shown in
FIG. 1
, an input circuit section
502
is connected through a wiring
508
to a bonding pad
500
. A plurality of MOS-type capacitance elements
504
,
505
and
506
are located adjacently to the bonding pad
500
. A lower electrode of these MOS-type capacitance elements
504
,
505
and
506
is a grounded silicon substrate. Respective upper electrodes are provided on the silicon substrate through dielectric film formed of silicon oxide. The respective upper electrodes are connected through fuses (not shown) to the bonding pad
500
.
Since the fuses of the MOS-type capacitance elements
504
,
505
are not cut off, the capacitance (capacities) thereof are connected to the bonding pad
500
. Since the fuse of the MOS-type capacitance element
506
is cut off, the capacitance of the MOS-type capacitance element
506
is not connected to the bonding pad
500
. In this way, the utilization of the fuse enables the connected capacitance value to be adjusted.
However, such an MOS-type capacitance element usually requires a large area and separately requires a process of forming itself. Here, also in a case of using a PN junction type capacitance element instead of the MOS-type capacitance elements
504
,
505
and
506
, a large area is typically required, and a process of forming itself is separately required.
The inventor of the present invention noticed that an input circuit of the input circuit section was composed of insulated gate field effect transistors (hereafter, referred to as MOS-transistors). As a result, the inventor of the present invention thought that the MOS-transistors as capacitance adjusting elements (MOS-transistors instead of the MOS-type capacitance elements
504
,
505
and
506
) should be formed, separately from the MOS-transistors for operating the input circuit section (the MOS-transistor of the above-mentioned input circuit).
The MOS-transistors as capacitance adjusting elements is formed with the present device process of the MOS-transistor. Thereby a gate oxide film serving as a capacitance insulating film of the capacitance adjusting element can be thinned to about 10 nm to thereby reduce an area occupied by the capacitance adjusting element. Moreover, it can be formed simultaneously with the MOS-transistor for operating the input circuit section. Thus, the process of forming the capacitance adjusting element is not additionally required.
For example, if using the device process to form the capacitance adjusting element composed of the MOS-transistors each having a gate oxide film of about 10 nm, the area thereof can be reduced to ⅙ or less of an area of a PN junction type capacitance element having the same performance.
In this case, it is necessary that an input protecting resistor is provided between the bonding pad and each of the MOS-transistor for operating the input circuit section and the MOS-transistor as the capacitance adjusting element, to protect the electrostatic breakdown in each gate oxide film.
Here, a delay amount when an input signal entered to the bonding pad is transmitted to the input circuit section is determined by a product of a resistor value R and a capacitance value C between the bonding pad and the input circuit section.
A value of a parasitic resistance of the wiring is sufficiently smaller than the resistor value of the input protecting resistor. Thus, the resistor value R is determined in accordance with a resistor value R
P
of the input protecting resistor. On the other hand, the capacitance value C includes a parasitic capacitance C
A
of element and wiring which is parasitic at a node (contact) between the input circuit section and the input protecting resistor and a capacitance value C
B
of the MOS-transistor serving as the capacitance adjusting element. Hence, the input signal entered to the bonding pad is delayed by a time corresponding to a time constant R
P
×(C
A
+C
B
) when the input signal is transmitted to the input circuit section.
FIG. 2
shows a signal wave form at this time. In
FIG. 2
, a symbol
610
denotes a signal wave form in the bonding pad. A symbol
620
denotes a signal wave form in the input circuit section transmitted under the delay of the time corresponding to the time constant R
P
×(C
A
+C
B
).
In
FIG. 2
, an input level is indicated in a typical LVTTL (Low Voltage Transistor-Transistor Logic) interface. As shown in a delay time
600
of
FIG. 2
, a signal
610
from external environment has a large delay amount in the device, and it is then transmitted to the input circuit section.
Actually, let us estimate this delay amount in a case of a 64 MSDRAM (64 megabits of Synchronous Dynamic Random Access Memory) which is presently typically used. As a standard value of the capacitance of the input terminal, its upper limit is defined as 4 pF, its lower limit is defined as 2.5 pF, and its intermediate value is 3.3 pF. In a high speed DRAM such as a SDRAM and the like, the signal delay in the device after the input protecting resistor causes an access speed value of the device to be increased and also causes the performance to be deteriorated.
Thus, the layout is typically designed such that the bonding pad and the input circuit section are as close as possible to each other, so as to suppress the parasitic capacitance C
A
of the device and the wiring which is parasitic at the node between the input circuit section and the input protecting resistor. In a case of 64 MSDRAM, the parasitic capacitance C
A
is about 0.1 pF.
On the other hand, parasitic capacitance values at a pad, an input protecting element, a lead frame and the like between the bonding pad and the input circuit of the device other than the above-mentioned parasitic capacitance C
A
are about 1.7 pF. Thus, in order to satisfy the standard value, it is necessary to further add (connect) a capacitance C
B
of about 1.5 pF to thereby set the capacitance of the input terminal to the intermediate value 3.3 pF in total. The value R
P
of the input protecting resistor is about 350 &OHgr;. Hence, the delay time of the signal in the device is represented in time constant as follows:
350 &OHgr;×(0.1 pF+1.5 pF)=560 pS.
This value is large to an extent that it can not be ignored for 2.0 nS and 1.0 nS of the setup and hold standard values with regard to an input signal.
These delay amounts are generated as the relative delay time of the device operation with respect to the signal entered in the device. Thus, they are regarded as the deterioration of the performance of the device. As mentioned above, the conventional technique shown in
FIG. 1
needs the large area in order to form the capacitance adjusting element. Thus, the integration degree is sacrificed. Also, it additionally needs the process of forming the capacitance adjusting element. Hence, the manufacturing process becomes complex, which results in interference with reduction of a manufacturing cost.
On the other hand, if trying to utilize the device process of the MOS transistor directly when forming the capacitance adjusting element,
Cunningham Terry D.
NEC Corporation
Nguyen Long
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