Semiconductor device utilizing a side wall to prevent...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S751000, C257S764000, C257S778000, C257S779000, C257S781000, C028S180000

Reexamination Certificate

active

06528881

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a solder ball formed on an electrode pad and a method for manufacturing the same semiconductor device.
2. Description of the Related Art
In recent years, the miniaturization in size and reduction in cost of electronic appliances such as mobile telephones and notebook-sized personal computers have advanced, and a semiconductor device such as a large-scale integrated circuit and the like (hereinafter referred to as an LSI) to be built in these electronic appliances is required to be more miniaturized in size and more reduced in cost.
In order to meet such a demand as described above, a flip chip ball grid array (FCBGA) method has appeared which fixes solder balls on a plurality of electrode pads on an LSI, connects the solder balls directly to the corresponding electrodes of a wiring board and thereby joins the LSI electrically and mechanically to the wiring board. In an LSI using this method, the surface layer of an electrode pad is formed out of copper (Cu) in order to improve the affinity of a solder ball for the electrode pad and make the connectivity better.
A conventional semiconductor device using an FCBGA method is disclosed in Japanese Patent Laid-Open Publication No. Hei 10-261,642.
FIG. 19
is a magnified sectional view showing a solder ball forming portion of a semiconductor device described in this reference.
This semiconductor device comprises a bonding pad
41
formed on a semiconductor substrate
31
, a passivation film
33
formed around the bonding pad
41
, a barrier film
38
formed on the passivation film
33
and the bonding pad
41
, an electrode pad
39
formed on the barrier film
38
in the same flat shape as the barrier film
38
, and a solder ball
34
fixed on the electrode pad
39
. The barrier film
38
is formed out of Ti, TiW, Cr or TiN, and the electrode pad
39
is formed out of Cu for the above-mentioned reason.
In such a conventional semiconductor device manufacturing method as described above, since a solder ball
34
stops at the outer edge portion of a barrier film
38
as covering the whole of an electrode pad
39
when it is reflowed and is fixed on the electrode pad
39
nearly in the shape of a sphere due to its surface tension, the solder ball
34
is brought into contact with the outer edge portions of both the electrode pad
39
and the barrier film
38
. Namely, since solder is good in wettability with Cu and is poor in wettability with Ti (titanium), solder goes around onto the side surface of the electrode pad
39
made of Cu and stops going around at the boundary between the electrode pad
39
made of Cu and the barrier film
38
made of Ti.
Due to heating for the solder reflow, as shown in
FIG. 20
, tin (Sn) atoms
43
thermally diffuse and move from the interface between the solder ball
34
and the electrode pad
39
into the electrode pad
39
. The inventors have found that at this time, since the quantity of movement of Sn atoms
43
in the interface between the electrode pad
39
and the barrier film
38
is larger than the quantity of movement of them in the interface between the solder ball
34
and the electrode pad
39
, the Sn atoms
43
have moved to a considerably deep interior from the side surface of the electrode pad
39
.
And when patterning the electrode pad
39
by means of etching and the like, its outer edge portion is sometimes not vertical, but is slanted. As shown by a dashed line in
FIG. 20
, which is a magnified view of a joint portion of
FIG. 19
, when the outer edge portion of the electrode pad
39
is formed in a tapered shape, Sn atoms
43
of an Sn component thermally diffuse from the tapered portion of the electrode pad
39
and the Sn atoms
43
easily reach the boundary between the electrode pad
39
and the barrier film
38
.
For such a reason as described above, the inventors have found also that Sn atoms
43
existing in the interface between the electrode pad
39
and the barrier film
38
degrade the adhesion of the electrode pad
39
to the barrier film
38
.
Generally, a solder ball is fixed on a wiring board (not illustrated) by being reflowed at a temperature of 355 to 365 C. At this time, a strain is generated by the difference in thermal expansion coefficient between a semiconductor chip including a semiconductor substrate and a wiring board. At this time, when there is said degradation in adhesion, as shown in
FIG. 20
, exfoliation
42
occurs at the interface between the electrode pad
39
and the barrier film
38
. The exfoliation
42
triggers exfoliation of the solder ball
34
to cause a continuity failure, or triggers the increase of electric resistance to cause degradation in the manufacturing yield rate.
SUMMARY OF THE INVENTION
In consideration of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same which can prevent an electrode pad from exfoliating from a barrier film, improve the manufacturing yield rate, and improve the reliability of connection of a semiconductor device with a wiring board even if a strain caused by the difference in thermal expansion coefficient between the semiconductor device and the wiring board acts on a solder ball.
In order to attain the above object, according to a first aspect of the present invention, there is provided a semiconductor device comprising a barrier film, an electrode pad directly contacting the barrier film, a solder ball directly contacting the electrode pad, and a side wall film separating the solder ball from a boundary between the barrier film and the electrode pad.
According to a second aspect of the present invention, there is provided a semiconductor device comprising a wiring layer, an insulating layer on the wiring layer, an opening formed in the insulating layer to expose an upper surface of the wiring layer, a barrier film formed on an inner surface of the opening and on the insulating; an electrode pad formed on the barrier film, a side wall film formed on a side surface of the barrier film and a side surface of the electrode pad covering a boundary between the barrier film and the electrode pad, and a solder ball formed on the electrode pad.
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of forming an insulating layer on a wiring layer, forming an opening in the insulating layer, the opening exposing an upper surface of the wiring layer, forming a first conductive film on an inner surface of the opening and on the insulating layer, forming a second conductive film on the first conductive film, patterning the first and second conductive films to form a barrier film on the wiring layer and an electrode pad on the barrier film, forming a side wall film covering a boundary between the barrier film and the electrode pad on patterned edges of the barrier film and the electrode pad, and forming a solder ball on the electrode pad.
According to the present invention, based on the above constitution, since the solder ball does not contact the boundary between the electrode pad and the barrier film, it is possible to prevent a component of the solder ball from diffusing into an interface of the electrode pad and the barrier film. Therefore, it is possible to prevent the electrode pad from exfoliating from the barrier film.


REFERENCES:
patent: 5136364 (1992-08-01), Byrne
patent: 6107170 (2000-08-01), Sathe et al.
patent: 6133136 (2000-10-01), Edelstein et al.
patent: 6187680 (2001-02-01), Costrini et al.
patent: 2002/0003302 (2002-01-01), Watanabe et al.
patent: 57-90963 (1982-06-01), None
patent: 6-21218 (1994-01-01), None
patent: 7-297149 (1995-11-01), None
patent: 8-45939 (1996-02-01), None
patent: 9-199505 (1997-07-01), None
patent: 10-261642 (1998-09-01), None
patent: 11-186308 (1999-07-01), None
patent: 2000-299337 (2000-10-01), None

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device utilizing a side wall to prevent... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device utilizing a side wall to prevent..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device utilizing a side wall to prevent... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3072408

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.