Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-04-28
2001-03-13
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S692000, C257S695000, C257S780000, C257S668000, C257S680000, C257S675000
Reexamination Certificate
active
06201298
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device utilizing a wiring tape, such as BGA (Ball Grid Array) or CSP (Chip Size Package).
2. Description of the Related Art
In recent years, there have been growing demands for the increased number of pins and a miniaturization with regard to semiconductor devices. To meet the demand, there have been proposed semiconductor devices called BGA or CSP. An example of such a semiconductor device is disclosed in Japanese Patent Laid-Open No. 55447/1997.
FIGS. 1A
to
1
C show the disclosed semiconductor device,
FIG. 1A
is a vertical sectional view taken along a line C-C′ of
FIG. 1B
,
FIG. 1B
is a horizontal sectional view taken along a line A-A′ of
FIG. 1A
, and
FIG. 1C
is a horizontal sectional view taken along a line B-B′ of FIG.
1
A.
As shown in
FIGS. 1A
to
1
C, the disclosed semiconductor device has a construction that an electrode
101
a
of semiconductor integrated circuit element (hereinafter referred to as chip)
101
is connected to an inner lead
102
f
extending inside a frame portion of a TAB tape
102
, which in turn is adhered to a metallic support frame
107
, and chip
101
, both oh which are covered with a potting resins
106
. TAB tape
102
has a circuit pattern
102
a
and inner lead
102
f
which are formed by etching metallic foil adhered onto a base substrate (e.g., polyimide tape)
102
c
of a frame configuration. Circuit pattern
102
a
is covered with a cover resist
102
e
except a portion to be connected with an external terminal
104
.
In the above structure, the provision of a through hole for the connection between external terminal
104
and a support frame
107
in the frame portion of TAB tape
102
, will endow support frame
107
with a GND plane (ground plane) function.
Another semiconductor device such as shown in each of
FIGS. 2A
to
2
C has been proposed.
FIG. 2A
is a vertical sectional view taken along a line C-C′ of
FIG. 2B
,
FIG. 2B
is a horizontal sectional view taken along a line A-A′ of
FIG. 2A
, and
FIG. 2C
is a horizontal sectional view taken along a line B-B′.
The semiconductor device comprises a chip
201
, a single-layer wiring tape
202
and a molding resin
203
for maintaining an outer shape of the device. Chip
201
includes an internal electrode
201
a
which is connected to an external terminal (e.g., solder ball)
204
, via through hole
202
b
in a base substrate
202
c
of a wiring tape
202
, and a circuit pattern
202
a
on base substrate
202
c
. Circuit pattern
202
a
is covered with a cover resist
202
e
except a portion to be connected with external terminal
204
and a portion forming through hole
202
b
. Electrode
201
a
on chip
201
and through hole
202
b
of wiring tape
202
are connected to each other by a bump. This connecting method is called an inner bump bonding (IBB) method. Wiring tape
202
and chip
201
are closely bonded to each other with an adhesive material
202
d
provided in wiring tape
202
by employing a hot pressing method. Chip
201
is covered by a molding resin
203
which is formed by employing a transfer molding method.
Unlike the semiconductor device described in the foregoing publication which uses TAB tape, the above structure enables external terminals to be arranged even on an area occupied by the chip, thus making a length of a wiring pattern for the connecting between the internal electrode and the external terminal shorter. This result in improved electrical characteristics as well as improved characteristics of radiating heat to a mounted substrate. In addition, unlike the inner lead of TAB tape, the external terminals can be freely arranged.
An approach to improve electrical characteristics such as noise reduction in the semiconductor device shown in
FIGS. 2A
to
2
C, is that GND plane or power plane is provided on an outer periphery of base substrate
202
c
of wiring tape
202
, and a wiring pattern is provided from a ground electrode on chip
201
to the GND plane(or from a power electrode on the chip to the power plane), passing between pads to be connected with the external signal terminal.
However, a further increase in the number of pins causes a pitch between the pads to be connected with the external signal terminal to be smaller. Thus, there is a limit on the number of wiring patterns which can be passed between the pads, making it difficult to provide the wiring pattern for GND and the wiring pattern for a power source between the pads. Namely, when the number of pins further increases, improvement of electrical characteristics such as noise reduction may be impossible.
An approach to address the above problem may involve a multilayer structure of a wiring tape, that is, a signal layer, a GND layer, and a power layer. This approach is, however, disadvantageous in that a multilayered wiring tape is costly, and hence reducing the cost of products may be impossible.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of reinforcing a GND line or a power line and also capable improving a signal characteristics while utilizing a less expensive single-layer wiring tape.
It is an another object of the present invention to provide a semiconductor device adaptable to the increased number of pins.
According to the present invention, a single-layer wiring tape to which a chip is electrically connected by means of inner bump bonding (IBB) is adhered to a printed circuit board including a GND plane and a power plane. Wiring patterns of the wiring tape connected to a power electrode on the chip and a GND electrode on the chip, are first connected to the GND plane and the power plane by means of inner bump bonding, and then further connected through the GND plane and the power plane, to an external power terminal on the wiring tape and an external GND terminal on the wiring tape.
In such a configuration, since a GND layer and a power layer are provided not on the wiring tape but on the printed circuit board which surrounds the chip, wiring of the wiring tape can be specially used for signal wiring. Accordingly, if the signal wiring is arranged at a higher density, it will be possible for the device to be adaptable to an increase in the number of pins. Conversely, if wiring pitches are made larger, it is possible to reduce costs of the wiring tape and noises.
Also, if large GND and power layers are separated, mutual impedance can be reduced.
Furthermore, the printed circuit board is less expensive because it is of simple structure which includes only GND and power planes without any high-density signal wiring. The connection between the printed circuit board and the wiring tape can also be made with ease by employing the same IBB method as the connection between the printed circuit board and the electrode on the chip. Thus, costs can be reduced remarkably over the case in the multilayer wiring tape.
The above and other objects, features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.
REFERENCES:
patent: 5776796 (1998-07-01), Distefano et al.
patent: 9-55447 (1997-02-01), None
patent: 409055447 (1997-02-01), None
patent: 10-256420 (1998-09-01), None
Kata Keiichiro
Sato Ryoji
Takeuchi Masanori
Hutchins, Wheeler & Dittmar
Loke Steven
NEC Corporation
Thai Luan
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