Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-03-27
2001-09-11
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S111000, C327S291000
Reexamination Certificate
active
06288585
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and particularly relates to a semiconductor device which adjusts a data-signal output timing based on a clock signal.
2. Description of the Related Art
Synchronous semiconductor devices such as an SDRAM (synchronous dynamic random access memory) operate in synchronism with a reference clock signal that is supplied thereto from an exterior of the device, or operate while keeping a predetermined phase relation with the reference clock signal. To achieve such synchronization, semiconductor devices have a control-clock-signal generation circuit provided therein for the purpose of adjusting internal operation timings.
One example of such a control-clock-signal generation circuit is a DLL (delay locked loop) circuit, which adjusts a propagation delay of a reference clock signal inside the device. The DLL circuit typically includes a variable-delay unit for delaying a reference clock signal to output a control clock signal having a predetermined timing, and includes a delay-adjustment unit for adjusting the delay of the reference clock signal based on the phase comparison between the reference clock signal and the delayed reference clock signal.
The control clock signal that is output from the DLL circuit is supplied to an output circuit via a clock buffer where the output circuit outputs a data signal, so that the control clock signal controls the operation timing of the output circuit. Such a DLL circuit has a configuration such as that disclosed in Japanese Patent Laid-open Application No. 10-112182.
In general, a DLL circuit uses a dedicated power voltage in order to prevent its operation from being affected by power noise. A clock buffer provided between the DLL circuit and an output circuit, however, utilizes an internally reduced power voltage that is also used by other circuits provided nearby.
Unfortunately, the internally reduced power voltage may suffer voltage fluctuation. When this happens, a control clock signal, which is supplied from the DLL circuit to the output circuit via the clock buffer, may have jitters because the clock buffer uses the internally reduced power voltage. Jitters end up being fed back to the DLL circuit, thereby reducing phase adjustment accuracy of the DLL circuit.
To avoid this, the clock buffer may be designed to use the same dedicated power voltage that is used by the DLL circuit. A layout restriction of the semiconductor device makes this option difficult. Further, such a design ends up creating noise in the dedicated power voltage provided for the DLL circuit. Noise in the power voltage for dedicated use by the DLL circuit results in a lower accuracy of phase adjustment in the DLL circuit.
Decreases in adjustment accuracy of the DLL circuit are generally main factors that degrade performance of the semiconductor devices.
Accordingly, there is a need for a semiconductor device which can reduce influence of power noises do as to adjust a signal-output timing based on an accurate control clock signal.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor device receiving a stable external power voltage including a reduced-voltage-generation circuit which generates an internally reduced power voltage, a miscellaneous circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.
In the semiconductor device described above, the clock-delivery circuit operates based on the external power voltage, so that the clockdelivery circuit can provide an accurate internal clock signal to the output circuit, and the output circuit can output the data signal at proper and accurate output timings that are not affected by power noises.
According to another aspect of the present invention, a semiconductor device includes a reduced-voltage-generation circuit which generates an internally reduced power voltage by reducing an external power voltage supplied from an exterior of the device, a miscellaneous circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to the exterior of the device at output timings responsive to the internal clock signal, a clock buffer circuit which buffers a clock signal supplied from the exterior of the device to supply the clock signal to the clock-control circuit, and operates solely based on the external power voltage; and buffer circuits which buffer signals supplied from the exterior of the device, and operate based on the internally reduced power voltage.
In the semiconductor device described above, the reduced-voltage-generation circuit is provided for the purpose of reducing power consumption. In this configuration, however, the clock buffer circuit that buffers the clock signal to be supplied to the clock-control circuit uses the external power voltage as its power voltage. The clock buffer circuit is thus unaffected by the fluctuation of the internally reduced power voltage, and can supply a stable and accurate clock signal to the clock-control circuit. This insures that the output circuit outputs the data signal at accurate output timings.
According to another aspect of the present invention, a semiconductor device includes a reduced-voltage-generation circuit which generates an internally reduced power voltage by reducing an external power voltage supplied from an exterior of the device, a miscellaneous circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, first buffer circuits which buffer first signals supplied from the exterior of the device, and operate solely based on the external power voltage, and second buffer circuits which buffer second signals supplied from the exterior of the device, and operate based on the internally reduced power voltage, wherein the first signals are required to be more accurate in timing than are the second signals.
In the semiconductor device described above, the reduced-voltage-generation circuit is provided for the purpose of reducing power consumption. In this configuration, however, the first buffer circuits for buffering the first signals that are required to meet relatively rigorous timing standards use the external power voltage as its power voltage. The first buffer circuits are thus unaffected by the fluctuation of the internally reduced power voltage, and can supply the first signals that maintain accurate timings.
REFERENCES:
patent: 6169435 (2001-01-01),
Bando Yoshihide
Hara Kota
Shinozaki Naoharu
Taniguchi Nobutaka
Tomita Hiroyoshi
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Zweizig Jeffrey
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