Semiconductor device using a plurality of...

Details Semiconductor device using a plurality of... Semiconductor device using a plurality of...

2009-02-13

2011-11-15

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Layout editor

C716S101000, C716S114000, C716S126000

Reexamination Certificate

active

08060854

ABSTRACT:
A plurality of third fixed potential lines are wired in parallel. A group of high-potential-side fixed potential lines containing a first fixed potential line and a second fixed potential line are wired in a plurality at predetermined intervals in a direction perpendicular to the third fixed potential line. In a layout region, surrounded by a pair of adjacent third fixed potential lines and a pair of groups of adjacent high-potential-side fixed potential lines, where a first element or a second element is arranged, either one of the first fixed potential line and the second fixed potential line is wired between the pair of third fixed potential lines. In a layout region used for second elements, a second fixed potential line connecting a pair of second fixed potential lines contained respectively in a pair of groups of high-potential-side fixed potential lines that form the layout region is wired between a pair of third fixed potential lines that form the layout region.

REFERENCES:
patent: 6898109 (2005-05-01), Hirose et al.
patent: 7002866 (2006-02-01), Hirose et al.
patent: 11-224901 (1999-08-01), None

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