Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-10-24
2006-10-24
Mai, Son (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185130, C365S185200
Reexamination Certificate
active
07126855
ABSTRACT:
A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
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Commonly assigned U.S. Appl. No. 09/478,057, filed Jan. 5, 2000 and 09/523,729, filed Mar. 18, 1999.
Hara Tokumasa
Hiramatsu Tatsuya
Honda Yasuhiko
Ikeda Takafumi
Kato Hideo
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Mai Son
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