Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-11-16
2003-01-28
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S189040, C365S230050
Reexamination Certificate
active
06512693
ABSTRACT:
RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Applications No. H11-129321, filed on May 10, 1999, and 2000-65397, filed on Mar. 9, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention relates generally to a semiconductor device, such as an electrically rewritable nonvolatile semiconductor memory device (EEPROM flash memory). More specifically, the invention relates to a flash memory system capable of simultaneously executing a data write or erase operation and a data read operation.
2. Description of The Related Background Art
Conventionally, there are various electronic systems wherein a plurality of memory devices are incorporated. For example, there is an electronic system wherein an EEPROM flash memory and an SRAM are incorporated to store data of the flash memory in the SRAM to exchange data between a CPU and the flash memory via the SRAM and to be capable of directly rewriting data of the flash memory without passing through the SRAM.
On the other hand, there is recently known a memory system called a read while write (RWW) type memory system capable of reading data out from a certain memory region while writing or erasing data in another memory region in order to reduce the number of memory chips necessary for the system. In order to form a memory device of this type, completely independent two memory regions may be simply provided in the memory device.
However, if the independently accessed regions are only simply provided in the memory device, there are problems as an RWW type memory system. First, since each of the memory regions independently requires a decoder and a sense amplifier, the layout area thereof is large. Secondly, if bit lines and word lines are continuously arranged independently every one of the memory regions, it is not possible to divide each of the memory regions into blocks to read and write data every block. That is, the range of the parallel execution of a data read operation and a data write operation is fixed, so that the system can not be applied to many uses. In order for the system to be applied many uses, a plurality of kinds of systems having different capacities of memory regions must be prepared.
In a conventional flash memory capable of simultaneously executing a data write or erase operation and a data read operation, a memory cell array is physically fixed to two banks. For example, considering a 32-Mbit flash memory chip, the capacity thereof is fixed so that one of the banks has 0.5 Mbits and the other bank has 31.5 Mbits. Therefore, users must newly buy another chip when requiring a different bank size.
In addition, as a circuit construction, dedicated address and data lines are provided every bank. When a write or erase operation is executed in blocks of one of banks, the power supply line of the one of the banks is connected to a writing or erasing power supply line by a power supply switch, and the power supply line of the other bank is connected to a reading power supply side. If the opposite operation instruction is inputted, each of the banks is connected to the power supply line on the opposite side by a corresponding one of the power supply switches.
Moreover, a set of sense amplifiers for detecting memory cell data are provided exclusively for each of the banks. For that reason, although it is possible to execute a read operation from memory cells in one of the banks while executing a write or erase in blocks in the other bank, it is impossible to simultaneously execute a write or erase operation and a read operation in the same bank.
In addition, since the banks are physically fixed, there is a severe limit to addresses capable of being simultaneously executed, and the size of each of the banks is also fixed, so that the degree of freedom is very low.
SUMMARY OF THE INVENTION
a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase, each of said memory cells being an electrically rewritable nonvolatile memory cell;
a core selecting portion configured to select an optional number of cores from said plurality of cores for writing or erasing data;
a data writing portion configured to write data in a selected memory cell in a core selected by said core selecting portion;
a data erasing portion configured to erase data from a selected block in a core selected by said core selecting portion;
a data reading portion configured to read data out from a memory cell in a core which is not selected by said core selecting portion; and
a bank setting memory circuit configured to select an optional number of cores of said plurality of cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of said first and second banks while a data write or erase operation is carried out in the other of said first and second banks.
According to another aspect of the present invention, a nonvolatile semiconductor memory device having a power supply control circuit for detecting an internal power supply voltage to hold a transition in the internal power supply voltage at a set level,
wherein said power supply control circuit has a dummy load capacity selectively connected in accordance with a load capacity of an internal power supply.
According to a further aspect of the present invention, a nonvolatile semiconductor memory device having a power supply control circuit for detecting an internal power supply voltage to hold a transition in the internal power supply voltage at a set level,
wherein said power supply control circuit has a circuit for changing an internal power supply driving capability in accordance with a load capacity of an internal power supply.
According to a still further aspect of the present invention, a semiconductor device comprising:
a plurality of functional blocks, each of which is arranged as a certain lump of circuit functions;
a signal line, arranged in a region of each of said functional blocks, for exchanging a signal between each of said functional blocks and the outside; and
a common bus line which is provided on a region of said plurality of functional blocks and commonly for said plurality of blocks and which is connected to said signal line via a contact.
According to still further aspect of the present invention, a nonvolatile semiconductor memory device which has the arrangement of a plurality of cores comprising a set of electrically rewritable nonvolatile memory cells and which is capable of reading data in an optional core of said plurality of cores while rewriting/erasing data in another optional core of said plurality of cores, said nonvolatile semiconductor memory device comprising:
a first data comparator circuit for comparing current of a first data line, which is selected in a verify read operation for data write/erase in one core of said plurality of cores, with current of a first reference signal line;
a second data comparator circuit for comparing current of a second data line, which is selected in a usual data read operation in the other core of said plurality of cores, with current of a second reference signal line;
first and second current source transistors for allowing a constant current to pass through each of said first and second reference signal lines; and
a reference constant current source circuit for driving said first and second current sources in parallel.
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U.S. patent application Ser. No. 09/478,057, Kato, filed Jan. 2000.
U.S. patent application Ser. No. 09/523,729, Kuriyama, filed Mar. 2000.
Hara Tokumasa
Hiramatsu Tatsuya
Honda Yasuhiko
Ikeda Takafumi
Kato Hideo
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Mai Son
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