Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-05-03
2002-04-23
Mai, Son (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S189040, C365S185110, C365S185130, C365S185290
Reexamination Certificate
active
06377502
ABSTRACT:
RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. § 119 to Japanese Patent Applications No. H11-129321, filed on May 10, 1999, and 2000-65397, filed on Mar. 9, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device, such as an electrically rewritable nonvolatile semiconductor memory device (EEPROM flash memory). More specifically, the invention relates to a flash memory system capable of simultaneously executing a data write or erase operation and a data read operation.
2. Description of the Related Background Art
Conventionally, there are various electronic systems wherein a plurality of memory devices are incorporated. For example, there is an electronic system wherein an EEPROM flash memory and an SRAM are incorporated to store data of the flash memory in the SRAM to exchange data between a CPU and the flash memory via the SRAM and to be capable of directly rewriting data of the flash memory without passing through the SRAM.
On the other hand, there is recently known a memory system called a read while write (RWW) type memory system capable of reading data out from a certain memory region while writing or erasing data in another memory region in order to reduce the number of memory chips necessary for the system. In order to form a memory device of this type, completely independent two memory regions may be simply provided in the memory device.
However, if the independently accessed regions are only simply provided in the memory device, there are problems as an RWW type memory system. First, since each of the memory regions independently requires a decoder and a sense amplifier, the layout area thereof is large. Secondly, if bit lines and word lines are continuously arranged independently every one of the memory regions, it is not possible to divide each of the memory regions into blocks to read and write data every block. That is, the range of the parallel execution of a data read operation and a data write operation is fixed, so that the system can not be applied to many uses. In order for the system to be applied many uses, a plurality of kinds of systems having different capacities of memory regions must be prepared.
In a conventional flash memory capable of simultaneously executing a data write or erase operation and a data read operation, a memory cell array is physically fixed to two banks. For example, considering a 32-Mbit flash memory chip, the capacity thereof is fixed so that one of the banks has 0.5 Mbits and the other bank has 31.5 Mbits. Therefore, users must newly buy another chip when requiring a different bank size.
In addition, as a circuit construction, dedicated address and data lines are provided every bank. When a write or erase operation is executed in blocks of one of banks, the power supply line of the one of the banks is connected to a writing or erasing power supply line by a power supply switch, and the power supply line of the other bank is connected to a reading power supply side. If the opposite operation instruction is inputted, each of the banks is connected to the power supply line on the opposite side by a corresponding one of the power supply switches.
Moreover, a set of sense amplifiers for detecting memory cell data are provided exclusively for each of the banks. For that reason, although it is possible to execute a read operation from memory cells in one of the banks while executing a write or erase in blocks in the other bank, it is impossible to simultaneously execute a write or erase operation and a read operation in the same bank.
In addition, since the banks are physically fixed, there is a severe limit to addresses capable of being simultaneously executed, and the size of each of the banks is also fixed, so that the degree of freedom is very low.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a nonvolatile semiconductor memory device having a plurality of cores which are a set of blocks serving as a unit of data erase, and capable of simultaneously executing a data write or erase operation in an optional core and a data read operation in another optional core.
It is another object of the present invention to provide a nonvolatile semiconductor memory device capable of setting the size of each of banks, each of which is a range of optionally selected cores, and of simultaneously executing a data write or erase operation and a data read operation in two banks.
It is a further object of the present invention to a semiconductor device having a chip size which can be decreased by efficiently arranging a common bus line with respect to a plurality of functional blocks.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor device comprises: a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase, each of the memory cells being an electrically rewritable nonvolatile memory cell; core selecting portion configured to select an optional number of cores from the plurality of cores for writing or erasing data; data writing portion configured to write data in a selected memory cell in a core selected by the core selecting portion; data erasing portion to erase data from a selected block in a core selected by the core selecting portion; and data reading portion configured to read data out from a memory cell in a core which is not selected by the core selecting portion.
According to the present invention, it is possible to obtain a flash memory of a free core system capable of selecting an optional core from a plurality of cores, each of which comprises one block or a set of a plurality of blocks, to write or erase data in the selected core while reading data out from another optional core.
According to another aspect of the present invention, a semiconductor device comprises: a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase, each of the memory cells being an electrically rewritable nonvolatile memory cell; a bank setting memory circuit for selecting an optional number of cores of the plurality of cores as a first bank and for setting the remaining cores as a second bank; core selecting portion configured to select an optional number of cores from the plurality of cores for writing or erasing data in each of the first and second banks; bank busy output circuits for outputting a bank busy output indicating that one of the first and second banks is in a data write or erase mode, on the basis of the core selecting portion and data stored in the bank setting memory circuit; data writing portion configured to write data in a selected memory cell of one of the first and second banks; data erasing portion configured to erase data from a selected block of one of the first and second banks; and data reading portion configured to read data out from one of the first and second banks, which is not in the data write or erase mode.
According to the present invention, it is possible to obtain a flash memory of a free bank system capable of optionally setting a bank size by causing a bank setting memory circuit to set optionally selected cores as a first bank and to set the remaining cores as a second bank, so that it is possible to read data in the second bank while writing or erasing data in optional blocks in the first bank.
Throughout the specification, the term “core” means a set of blocks serving as a unit of data erase as described above. Specifically, the “core” means a lump of a plurality of blocks sharing address lines, power supply lines and data lines, and a set of a plurality of blocks, to one block of which acc
Hara Tokumasa
Hiramatsu Tatsuya
Honda Yasuhiko
Ikeda Takafumi
Kato Hideo
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Mai Son
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