Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2002-04-23
2003-07-01
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C365S200000, C365S201000, C365S222000
Reexamination Certificate
active
06586823
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a configuration of a semiconductor device having a plurality of semiconductor integrated circuit chips of various types assembled in one package.
2. Description of the Background Art
In accordance with down-sizing of apparatus in which a semiconductor integrated circuit chip is mounted such as in cellular phones, the so-called three-dimensional packaging technology of mounting a plurality of semiconductor integrated circuit chips in a package and sealing the package has been developed. The usage of such 3-dimensional packaging technology allows a memory of larger capacity and a multifunction system of a higher level to be sealed in a package that has a profile identical to that of an existing product. There was an advantage that the apparatus can be fabricated using currently-available packaging apparatuses with the functions of the apparatus being improved.
In the application to a cellular phone, for example, the technique of sealing the multilayers of a flash memory chip for program storage and a static type random access memory (referred to as SRAM hereinafter) chip for data backup within one package has been realized. By using such 3-dimensional packaging technique, it is possible to realise a system that stacks a microcomputer chip and a dynamic random access memory (referred to as DRAM hereinafter) chip to be mounted in one package.
This three-dimensional packaging technique contributes, not only to down-sizing of the apparatus, but also to increase the speed of computers and communication apparatuses. This is because signals can be transmitted at high speed by mounting and wiring chips in a 3-dimensional manner to reduce the wiring length.
FIG. 17
shows the concept of the process of stacking two semiconductor memory chips
9010
and
9030
within one package as an example of the above-described 3-dimensional packaging.
It is assumed that the first semiconductor memory chip
9010
is, for example, a flash memory, whereas the second semiconductor memory chip
9030
is an SRAM.
Semiconductor memory chip
9010
includes a memory cell array
9022
with a plurality of spare memory cells in addition to a plurality of proper memory cells, a control circuit
9016
receiving a signal from an input terminal group
9012
that receives an externally applied control signal and address signal to control the operation of semiconductor memory chip
9010
, a row select circuit
9018
selecting a row in memory cell array
9022
under control of control circuit
9016
, a column select circuit
9020
selecting a column to read and write data, a data input/output circuit
9024
receiving and providing to column select circuit
9022
the data applied from data input/output terminal
9014
, or receiving and providing to a data input/output terminal
9014
data read out from column select circuit
9020
, and a replacement data retain circuit
9026
prestoring a defective address where a defective memory cell found in memory cell array
9022
in a test mode is located, and selecting a spare memory cell instead of a defective proper memory cell when an address signal selecting the defective memory cell is applied from an external source.
Semiconductor memory chip
9030
has a structure basically similar to that of the above-described semiconductor memory chip
9010
. In
FIG. 17
, only a replacement data retain circuit
9032
storing a defective address to replace a defective memory cell with a proper memory cell in semiconductor memory chip
9030
is depicted. Other structural components are not illustrated.
As shown in
FIG. 17
, in a multichip module storing a plurality of semiconductor memory chips
9010
and
9030
in one package, each semiconductor memory chip is first subjected to testing in the wafer state according to individual testing standards. In order to replace a defective memory cell with a redundant memory cell and repair the defective memory, programming of the defective address is effected in respective replacement data retain circuits
9026
and
9032
to repair defective memory cell. Then, testing is carried out again to select the semiconductor memory chip determined to include memory cells that are all good.
After sorting out the semiconductor memory chips in the wafer state, the chips are separated by dicing. A multichip module is assembled by combining the good semiconductor memory chips. In semiconductor memory chip
9010
of
FIG. 17
, input signal terminal
9012
and data input/output terminal
9014
are depicted at only one side of the chip for the sake of simplification. In practice, such terminals are disposed over at least one side around the chip.
Thus, with respect to a lead frame
9100
in the multichip module, semiconductor memory chip
9010
is connected by chip-wire bonding
9120
. Chip
9030
stacked on chip
9010
is bonded with the pad of chip
9010
through chip wire bonding
9110
.
A lead
9130
extends outward from lead frame
9100
to transfer signals or data with a source external to the package. Lead frame
9100
and chips
9010
and
9030
shown in
FIG. 17
are, in practice, sealed within a package or a resin mold.
In forming a multichip model by the above process, the defective address is programmed in replacement data retain circuits
9026
and
9032
by burning out the fuse or the like through a laser trimming device during wafer testing in the defective memory cell repair process of each chip. In each chip, an address replacement function is rendered effective to perform a redundancy replacement repair.
In such a multichip module, testing is also carried after the packaging process. The package in which all the memories of various types are good is sorted out as an acceptable product.
The above description is directed to the case where two semiconductor memory chips, for example, are sealed in one package. There is also a case where more semiconductor memory chips are sealed in one package.
Consider the case where three chips, for example, are sealed in one package. Assuming that the yield in the testing after packaging is y1% for the first chip, y2% for the second chip and y3% for the third chip, the total yield after packaging is degraded to (y1×y2×y3) %.
In other words, there is a possibility of a defect being produced before the assembly process (packaging process) ends even for chips that are determined to be acceptable in a wafer state. Such chips are taken as defective products since it cannot be repaired even if detection of a defective chip is carried out in the testing subsequent to the assembly process (packaging process). There was a problem that the total yield of the final product is degraded.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device that can have a defective bit found during or after the packaging process in a multichip module repaired to improve the total yield.
According to an aspect of the present invention, a semiconductor device includes a package, a hold member, a plurality of memory chips, a coupling member, a replacement information storage circuit, and a replacement storage control circuit.
The hold member is provided in the package. The plurality of memory chips are held by the hold member. Each memory chip includes a plurality of proper memory cells, a spare memory cell, a first storage circuit, an information replacement circuit, a replacement information input circuit, and a select circuit. The first storage circuit stores address information corresponding to a defective memory cell found during a fabrication process of a memory chip. The information replacement circuit can alter the address information output from the first storage circuit according to externally applied additional replacement information. The replacement information input circuit receives additional replacement information from outside the memory chip. The select circuit selects any of a proper memory cell and a spare memory cell according to the output from the information replacement circuit
Ohmura Ryuji
Sugiura Kazushi
Cieslewicz Aneta
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Pham Long
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