Semiconductor device testing system and method

Details Semiconductor device testing system and method Semiconductor device testing system and method

1999-07-07

2002-04-02

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06366109

ABSTRACT:

This patent application claims priority based on a Japanese patent application, H10-192050 filed on Jul. 7, 1998, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a system for testing semiconductor devices, and in particular to a semiconductor device testing system including a pin assignment convertor converting logical pin numbers and physical pin numbers of a test unit.
2. Description of the Related Art
FIG. 1
shows a conventional semiconductor device testing system inspecting a semiconductor device
72
. The semiconductor device testing system incorporates a workstation
10
, a tester body
20
, and a test head
30
, wherein the workstation
10
is connected to the tester body
20
, which is also connected to the test head
30
using a cable.
The tester body
20
includes a tester controller
40
and a test unit
22
, which has a pattern generator
50
and a wave shaper
60
. The test head
30
includes a measuring unit
80
and a semiconductor device insertion unit
70
on which the semiconductor device
72
lies.
The workstation
10
readies a test vector and test program used for inspecting the semiconductor device
72
using logical pin numbers, which are virtual pin numbers of the test unit
22
assigned in software. In addition to the test vector and the test program, a pin correspondence table is defined that is used for converting the logical pin numbers into the physical pin numbers assigned to the hardware of the test unit
22
. In the pin correspondence table, logical pin numbers correspond to respective physical pin numbers.
The test vector, the test program, and the pin correspondence table are compiled together. This compile converts logical pin numbers into physical pin numbers pursuant to the pin correspondence table. The compiled files are fed into the tester controller
40
. The tester controller
40
, which includes a dedicated processor managing or controlling hardware and software in the test system, prepares a data signal
44
and an address signal
42
to feed them into the pattern generator
50
. The address signal
42
designates the pins of the test unit
22
in terms of physical pin numbers.
The pattern generator
50
outputs the semiconductor device input signal
52
to the wave shaper
60
based upon the address signal
42
and the data signal
44
. When the wave shaper
60
receives the semiconductor device input signal
52
, it shapes the signal according to the characteristic of the semiconductor device
72
. After shaping, the wave shaper
60
feeds the semiconductor device input signal
62
to the semiconductor device insertion unit
70
.
Within the semiconductor device insertion unit
70
, the semiconductor device
72
receives the semiconductor device input signal
62
to feed an output signal
74
according thereto to the measuring unit
80
. The measuring unit
80
judges whether the semiconductor device
72
meets given criterion.
Generally, semiconductor chips are packed into a variety of packages each having a different wiring, in general. In other words, for example, even though two different packages each include the same semiconductor chip, the pin assignment of the first package will differ from that of the second. From viewpoint of function, a pin number for a given function in the former package is also different from a pin number for the same given function in the latter package.
As described above, the test vector and the test program are prepared pursuant to the virtual logical pin numbers. Meanwhile, the actual physical pin numbers depends upon semiconductor devices. Therefore, in order to inspect the semiconductor devices, the logical pin numbers are required to converted into the corresponding physical pin numbers in the test unit
22
for each semiconductor device.
As described above, the pin correspondence table, which denotes relationship between the logical pin numbers and the physical pin numbers, are compiled with the test vector and the test program. Here, the pin correspondence table is required to be prepared for each semiconductor device. As a result, the compile of the test vector and program, and the pin correspondence table needs to be executed for each semiconductor device.
Accordingly, in the conventional semiconductor device testing system, the workstation
10
manages compiled files for each kind of semiconductor device. Further, a request for improving a part of the test vector or the test program arises, not all of the compiled files prepared for a variety of semiconductor devices are not available for improvement because it is difficult to correct compiled test vectors or test programs. Rather, it is necessary to prepare a new test vector or program to recompile it with the pin correspondence table. The revised test vector or program is recompiled for each pin correspondence table, that is to say, for each semiconductor device, which requires far too much time.
Such increased processes also increased the risk of operator error. For example, the risk of compilation errors or of failure when managing compiled files is increased.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a semiconductor device testing system and method which overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to an aspect of the present invention, there is provided a semiconductor device testing system for testing a semiconductor device with a plurality of pins by applying a test signal, comprising: a tester controller that outputs generation data used for generating the test signal, a logical pin number of a logical pin to which the test signal is applied according to the generation data, and pin assignment data denoting a relationship between the logical pin number and a physical pin number of a physical pin to which the test signal is applied according to the semiconductor device; a pin assignment convertor that converts the logical pin number into the physical pin number based on the pin assignment data; and a test unit that uses the generation data to prepare the test signal for application to the physical pin designated by the physical pin number.
The test unit preferably includes a pattern generator that generates the test signal based upon the generation data.
The tester controller preferably notifies the pin assignment convertor of the logical pin number. The tester controller preferably replaces the pin assignment data with another pin assignment data. The tester controller preferably outputs to the pin assignment convertor a recognition bit used for determining whether or not the logical pin number and the physical pin number are converted.
The pin assignment convertor preferably includes a pin map memory that stores the pin assignment data. The pin map memory preferably includes a plurality of address pins notified of the logical pin number, and a plurality of data pins notifies of the physical pin number. The pin assignment convertor preferably determines whether or not the logical pin number and the physical pin number are converted, based upon the value of the recognition bit. The pin assignment convertor preferably includes a recognition decoder that receives the recognition bit from the tester controller, and the recognition decoder determines whether or not the logical pin number and the physical pin number are converted.
The semiconductor device testing system preferably further comprises a workstation including a monitor that displays the logical pin number.
According to another aspect of the present invention, there is provided a method of testing a semiconductor device using a test unit that prepares a test signal and has a plurality of logical pin numbers and a plurality of physical pin numbers, comprising: outputting the plurality of logical pin numbers and a generation data used for generating the

Affiliated with

Also associated with

Rating

Semiconductor device testing system and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device testing system and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device testing system and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2834914