Semiconductor device testing system

Details Semiconductor device testing system Semiconductor device testing system

2000-10-25

2003-01-14

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S081000, C702S117000, C702S118000, C702S123000

Reexamination Certificate

active

06507801

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device testing system for testing a semiconductor device, such as a semiconductor memory, and more particularly to a semiconductor device testing system for performing AC tests on the semiconductor device to evaluate operational functions of the device.
2. Description of the Prior Art
An electrical die sorting (EDS) process is one of the steps in fabricating a semiconductor device, such as a memory device, a non-memory device, or other similar devices. In general, semiconductor device testing systems are used during the EDS process to determine the electrical properties of a wafer-level semiconductor device. More specifically, during the EDS process, a semiconductor device testing system is used to conduct a series of wafer-level tests to evaluate the electrical properties and functions of the semiconductor device.
The EDS process itself is divided into two primary stages, a pre-laser stage and a laser repair stage. In the pre-laser stage, defective chips on the semiconductor wafer are screened to determine which of those chips can possibly be repaired. The addresses of the defective chips that can possibly be repaired are transmitted to the laser repair stage so that laser repair of those chips can be attempted. During the pre-laser stage, a prober is used to load and align the chips with testing pointers. Wafers are loaded into the prober to undergo a series of tests. DC tests are performed to evaluate the DC properties of the device, such as current and voltage levels. AC tests are also performed to determine operational functions of the device.
Both the AC and the DC tests are performed by a semiconductor device testing system during the EDS process. To perform the DC tests, the semiconductor device testing system generates a variety of electrical signals that are transmitted through PIN drivers to each pad of the semiconductor device. The semiconductor device testing system decodes the data obtained by these tests and determines whether the current, voltage, and other DC parameters are within acceptable performance levels.
The AC tests, on the other hand, are performed to analyze operational functions of the device, such as circuit operations, data storage, etc., under predetermined supply voltage margin, input voltage margin, timing margin, temperature, and humidity conditions. The AC tests for a DRAM device include, for instance, a refresh test, a functional test, a speed test, and a margin test. To perform the AC tests, wafer pads are loaded into the top portion of a chuck stage of the prober by vacuum absorption and are then placed onto a test board (or probing card) that has a plurality of testing pointers. A test head of the semiconductor device testing system contacts the test board to perform the wafer-level testing processes in accordance with a preset testing program.
As semiconductor circuits become more complicated, the number of CMOS transistors integrated onto each silicon chip increases proportionally. Accordingly, it is desirable to perform high-speed, highly precise, testing procedures during the EDS process, in addition to the normal testing procedures. Unfortunately, in conventional semiconductor device testing systems, there are only certain uniformly specified PIN drivers available to output the required testing signals. And because the testing capability of the semiconductor device testing system is directly related to the basic specifications of the PIN drivers, it is very difficult for conventional systems to operate above their basically specified functions. A conventional semiconductor device testing system that is configured to operate at a normal operational speed, therefore, cannot be used to perform tests at a higher operational speed. Conventionally, a separate, high-speed testing unit is consequently required to perform the high-speed tests on semiconductor devices.
According to the prior art, therefore, after a high-speed semiconductor memory device is tested at a first, normal operational speed using a normal-speed semiconductor device testing system, a separate high-speed testing unit must be used to perform tests at a second, higher operational speed. Unfortunately, the need for separate testing units results in the added expense of additional equipment. Also, because the normal and high-speed tests are performed sequentially, the need for separate testing equipment significantly increases the amount of time required to perform those tests.
It is therefore imperative to the industry that a semiconductor device testing system be developed that simplifies the process for testing a high-speed semiconductor device and reduces the time and expense of the overall testing process.
SUMMARY OF THE INVENTION
An object of the present invention is to enable a semiconductor device testing system that provides both normal and high-speed testing capabilities in a single testing unit.
Another object of the present invention is to enable a semiconductor device testing system that can perform normal and high-speed AC tests on a semiconductor memory device while decreasing the time and expense of the overall testing process.
A third object of the present invention is to provide a semiconductor device testing system and method, wherein high-speed PIN drivers are partly embedded in a conventional normal testing system to enable the performance of both high-speed and normal-speed testing operations by a single testing unit.
In order to accomplish the aforementioned objects, a semiconductor device testing system is configured to perform multiple tests on a semiconductor device during an EDS process. The semiconductor device testing system includes a system frame that includes both normal and high-speed testing formatters. A test head, that includes both normal PIN drivers and high-speed PIN drivers, is connected to the system frame. The normal PIN drivers are configured to operate at a first frequency to transmit signals required for normal-speed tests to a semiconductor device. The high-speed PIN drivers are configured to operate at a second frequency, higher than the first frequency, to transmit the signals required for high-speed tests to the semiconductor device. Normal and high-speed testing capabilities are thereby integrated into a single testing unit.
The integration of normal-speed and high-speed testing capabilities into a single testing unit improves the testing capability of the system while only minimally increasing the production cost of the system above the cost of the normal testing system alone. Furthermore, this integration allows the overall production costs for the normal and high-speed testing system to be reduced.
In accordance with the present invention, a method is also provided that allows a semiconductor device testing system to perform a first test at a normal speed, and a second test at a higher speed. The method includes using high-speed PIN drivers and normal PIN drivers as main PIN drivers on the test head of the semiconductor device testing system. Preformatted signals for performing high-speed operations are sent to the high-speed PIN drivers to perform the second test.


REFERENCES:
patent: 5384784 (1995-01-01), Mori et al.
patent: 5428754 (1995-06-01), Baldwin
patent: 6157200 (2000-12-01), Okayasu

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