Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2002-07-26
2003-04-15
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C714S700000
Reexamination Certificate
active
06549000
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus for testing various kinds of semiconductor devices including a semiconductor integrated circuit and determining whether the tested semiconductor device is a defective (failure) article or not, and more particularly, relates to such a semiconductor device testing apparatus having timing hold function which is capable of conforming the timing at which a test pattern signal is applied to each of terminals of a semiconductor device tinder test and the timing at which a response output signal outputted from each of terminals of the semiconductor device under test is fetched or read in, to a predetermined set value for each terminal.
2. Description of the Related Art
A prior semiconductor device testing apparatus for testing various kinds of semiconductor devices and determining whether the tested semiconductor device is a defective article or not is shown in FIG.
4
. Here, for clarity of the description, in
FIG. 4
is shown an outline of the construction of a semiconductor integrated circuit testing apparatus for testing a semiconductor integrated circuit (hereinafter, referred to as IC) which is a typical of semiconductor devices and determining whether the tested IC is a defective article or not.
The IC testing apparatus TES comprises, roughly speaking, a controller
11
, a pattern generator
12
, a timing generator
13
, a waveform generating part
14
, a logical comparator
15
, a driver
16
, an analog level comparator (hereinafter referred to as comparator)
17
, a failure analysis memory
18
, a logical amplitude reference voltage source
21
, a comparison reference voltage source
22
, and a device power source
23
.
The controller
11
is generally constituted by a computer system, in which a test program PM created by a user (programmer) is stored in advance, and the entire IC testing apparatus is controlled in accordance with the test program PM. The controller
11
is connected, via a tester bus BUS, to the pattern generator
12
, the timing generator
13
, and the like. Although not shown, the logical amplitude reference voltage source
21
, the failure analysis memory
18
, the logical amplitude reference voltage source
21
, the comparison reference voltage source
22
, and the device power source
23
are also connected to the controller
11
.
First of all, before the testing of an IC is started, various kinds of data are set by the controller
11
. After the various kinds of data have been set, the testing of an IC is started. When the controller
11
gives a test starting instruction or command to the pattern generator
12
, the pattern generator
12
starts to generate a pattern. The pattern generator
12
supplies test pattern data to the waveform generating part
14
, in accordance with the test program PM.
The timing generator
13
generates timing signals (clock pulses) for defining timings of rise and fall of the waveform of a test pattern signal applied to an IC to be tested (IC under test)
19
respectively, and also generates a timing signal (clock pulse) for a strobe pulse which defines a timing of a logical comparison between an expected value pattern signal and a response signal in the logical comparator
15
, and the like.
Timings and periods that those timing signals are to be generated are described in the test program PM created by a user, and it is arranged that a test pattern signal can be applied to the IC under test
19
with an operating period and at a timing designed or established by the user to actually operate the IC under test, and whether that operation of the IC under test is normal or not can be tested.
The waveform generating part
14
converts the test pattern data supplied from the pattern generator
12
into a test pattern signal having a real waveform. This test pattern signal is applied to the IC under test
19
via the driver
16
that amplifies the voltage of the test pattern signal to a waveform having an amplitude value set by the logical amplitude reference voltage source
21
.
A response signal read out from the IC under test
19
is compared with a reference voltage supplied from the comparison reference voltage source
22
in the comparator
17
, and it is determined whether or not the response signal has a predetermined logical level, i.e., whether or not the response signal has a predetermined logical H (logical high) voltage or logical L (logical low) voltage. A response signal determined to have the predetermined logical level is sent to the logical comparator
15
, where the response signal is compared with an expected value pattern signal outputted from the pattern generator
12
, and whether or not the IC under test
19
has outputted a normal response signal is determined.
In case that the IC under test
19
is a memory element, if the response signal does not coincide with the expected value pattern signal, the logical comparator
15
determines that the memory cell having an address of the IC under test
19
from which the response signal has been read out is defective (failure), and generates a failure signal indicating that fact. Usually, when the failure signal is generated, a writing of a failure data (generally logical “1” signal) in the failure analysis memory
18
applied to a data input terminal thereof is enabled, and the failure data is stored in an address of the failure analysis memory
18
specified by an address signal being supplied to the failure analysis memory
18
at that time.
The failure analysis memory
18
has its operating rate or speed and its memory capacity equivalent to those of the IC under test
19
, and the same address signal as the address signal applied to the IC under test
19
is also applied to this failure analysis memory
18
. In addition, the failure analysis memory
18
is initialized prior to the start of a testing. For example, when initialized, the failure analysis memory
18
has data of logical “0s” written in all of the addresses thereof. Every time a failure signal indicating that the anti-coincidence is generated from the logical comparator
15
during a testing of the IC under test
19
, a failure data of logical “1” indicating the failure of a memory cell is written in the same address of the failure analysis memory
18
as that of the memory cell of the IC under test
19
from which that anti-coincidence has occurred.
On the contrary, when the response signal coincides with the expected value pattern signal, the logical comparator
15
determines that the memory cell having an address of the IC under test
19
from which the response signal has been read out is not defective (pass), and generates a pass signal indicating that fact. Usually, this pass signal is not stored in the failure analysis memory
18
.
After the testing has been completed, the failure data stored in the failure analysis memory
18
are read out therefrom into a failure relief analyzer not shown, and it is determined, for example, whether a relief or repair of failure memory cells of the tested IC is possible or not.
Further, in
FIG. 4
, the block diagram is depicted such that the test pattern signal outputted from the driver
16
is applied to only one input terminal of the IC under test
19
, and that a response signal from one output terminal of the IC under test
19
is supplied to the comparator
17
. However, the number of drivers
16
provided is actually equal to the number of input terminals of the IC under test
19
, for example 512, and the number of comparators
17
provided is also equal to the number of output terminals of the IC under test
19
(since the number of input terminals provided is usually equal to the number of output terminals, the number of comparators
17
provided is equal to the number of drivers
16
provided). In addition, although the input terminals of the IC under test
19
are depicted, in
FIG. 4
, as separate terminals from the output terminals of the IC under test
19
, there are many cases in general that each terminal
Advantest Corporation
Cuneo Kamand
Gallagher & Lathrop
Kobert Russell M.
Lathrop, Esq. David N.
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