Semiconductor device testing apparatus and semiconductor...

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Reexamination Certificate

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C209S571000

Reexamination Certificate

active

06433294

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus suitable for testing one or more semiconductor devices, particularly one or more semiconductor integrated circuit elements (as will be referred to as IC or ICs hereinafter) which are typical examples of the semiconductor devices. More particularly, the present invention relates to a semiconductor device testing apparatus of the type in which semiconductor devices to be tested are transported, for testing, to a test or testing section where they are brought into electrical contact with a tester head (a component of the testing apparatus for applying and receiving various electrical signals for testing) to perform an electrical test of the semiconductor devices, followed by being carried out of the test section and then the tested semiconductor devices are sorted out into conformable or pass articles and unconformable or failure articles on the basis of the test results, and a semiconductor device testing system having a plurality of such semiconductor device testing apparatus.
2. Description of the Related Art
Many of semiconductor device testing apparatus (commonly called IC tester) for applying a test signal of a predetermined pattern to a semiconductor device to be tested, i.e. device under test (commonly called DUT) and measuring the electrical characteristics of the devices, have a semiconductor device transporting and handling or processing apparatus (commonly called handler) mounted thereto which transports semiconductor devices to a test section, brings them into electrical contact with a tester head in the test section, after the testing, carries the tested semiconductor devices out of the test section, and sorts them out into pass articles and failure articles on the basis of the test results. In the specification, the testing apparatus which comprises a combination of the IC tester and the handler mounted or connected thereto of the type described above is termed “semiconductor device testing apparatus”. In the following disclosure the present invention will be described by taking ICs typical of semiconductor devices for example for clarity of explanation.
As the density of elements integrated on a semiconductor substrate or chip in an IC becomes higher, the number of terminals or pins of the IC is increased, and it is difficult to test such an IC having a large number of terminals using an IC testing apparatus having a naturally dropping type handler mounted thereto in which ICs are caused to slide down in a sloped carrying path or groove by their gravities for testing the ICs. Therefore, the general trend in recent years is toward the use of an IC testing apparatus having a handler called “horizontal transporting system” mounted thereto which can transport ICs to any desired place or position by using suction head means utilizing a vacuum pump which may pick up one to several ICs at a time and X and Y direction transfer means.
There have been previously used in practice following two types of IC testing apparatus each having a horizontal transporting system handler mounted thereto.
(1) One type of the IC testing apparatus is arranged such that a tray on which many ICs are loaded in a plane is placed at a predetermined position of the testing apparatus, a predetermined number of ICs are picked up by suction from the tray by use of a suction head utilizing a vacuum pump (vacuum suction head), the ICs being attracted against the vacuum suction head are transported to a test section through a preheating/precooling section by use of X and Y direction transfer means for testing, and upon completion of the test the tested ICs are sorted out into conformable articles (pass articles) and unconformable articles (failure articles), and transferred onto the corresponding trays by use of X and Y direction transfer means.
(2) The other type of the IC testing apparatus is arranged such that many ICs are loaded in a plane on a general-purpose tray (customer tray) which is used by a user for conveying ICs or storing ICs at a predetermined place or the like in the outside of the testing apparatus, the general-purpose tray with the ICs loaded is placed at a loader section of the testing apparatus where the ICs are transferred from the general-purpose tray onto a test tray capable of withstanding high/low temperatures, the test tray is transported through a constant temperature chamber or thermostatic chamber to a test section where ICs are brought into electrical contact with a tester head in the state that they are being loaded on the test tray for performing a test, and upon completion of the test the test tray with the tested ICs loaded are transported through a temperature-stress removing chamber to an unloader section where the tested ICs are sorted out into pass articles and failure articles and transferred onto the corresponding trays to be reloaded thereon.
The IC testing apparatus having a handler of the former type (1) mounted thereto has a disadvantage that since the number of ICs which undergo a test at a time is limited to two to four, the processing speed is low, and hence a considerable time is required to test all ICs. That is, the IC testing apparatus of the type (1) is not suitable for processing at high speed. on the other hand, the IC testing apparatus having a handler of the latter type (2) mounted thereto has an advantage that since ICs can be brought into electrical contact with a tester head of the testing apparatus in the state that they are being loaded on the test tray in the test section, it is possible to test many of ICs such as 16, 32 or 64 at a time. Therefore, at present, an IC testing apparatus having a handler of the latter type (2) mounted thereto is being mainly used.
A description will be given first regarding the general construction of a conventional IC testing apparatus having a handler of the latter type (2) mounted thereto with reference to
FIGS. 4 and 5
. The illustrated IC testing apparatus comprises a chamber section
100
for testing ICs such as semiconductor memories which are loaded on a test tray TST and carried on the test tray TST, an IC storage section
200
where ICs which will undergo a test (i.e., ICs to be tested) are sorted out and the tested ICs are sorted out and stored in place, a loader section
300
where ICs to be tested which a user has beforehand loaded on a general-purpose tray (customer tray) KST are transferred and reloaded onto a test tray TST capable of withstanding high/low temperatures, and an unloader section
400
where the tested ICs which have been carried on the test tray TST out of the chamber section
100
subsequently to undergoing a test in the testing chamber
100
are transferred from the test tray TST to one or more general-purpose trays KST to be reloaded on the latter. The unloader section
400
is generally constructed to sort out the tested ICs by categories on the basis of the data of the test results and load them on the corresponding general-purpose trays.
The chamber section
100
comprises a constant temperature or thermostatic chamber
101
for receiving the ICs to be tested loaded on the test tray TST and imposing an intended high or low temperature stress to the ICs, a test or testing chamber
102
for effecting an electrical test on the ICs subjected to the temperature stress in the constant temperature chamber
101
, and a temperature-stress removing chamber
103
for removing the temperature stress of the ICs having been applied thereto in the test chamber
102
from the ICs. The test chamber
102
contains therein a tester head
104
of the testing apparatus, supplies various electric signals for testing via the tester head
104
to the ICs to be tested in electrically contact therewith, receives response signals from the ICs, and sends them to the testing apparatus.
Each of the test trays TST is moved in a circulating manner from the loader section
300
through the constant temperature chamber
101
of the chamber section
100
, the test chamber
102
of

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