Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-04-27
2003-08-05
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C438S017000, C716S030000
Reexamination Certificate
active
06604058
ABSTRACT:
This patent application claims priority from Japanese patent application No. 2000-131174 filed on Apr. 28, 2000, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus for testing a semiconductor device. In particular, the present invention relates to a semiconductor device testing apparatus that does not interrupt a test just after restarting of the test and also does not apply an input-signal pattern to the semiconductor device, which causes a match-fail, until the end of the test.
2. Description of the Related Art
FIG. 1
is a block diagram that shows a configuration of a pattern generator
10
of a conventional semiconductor device testing apparatus. The pattern generator
10
has a match-fail detecting unit
20
, a sequence control unit
40
, and a pattern data memory
50
. A control apparatus
210
controls each unit of the pattern generator
10
. Each unit of the pattern generator
10
receives a clock signal that is output from a reference clock generator
60
.
The semiconductor device testing apparatus is used for testing a logic IC such as a system LSI. In particular, the semiconductor device testing apparatus
100
can test a plurality of semiconductor devices at the same time. The pattern generator
10
generates an input-signal pattern
12
and an expectation value signal pattern
14
according to the predetermined control sequence. The input-signal pattern
12
is a signal to be input to a semiconductor device that is an object to be tested. The expectation value signal pattern
14
is a signal to be output from the semiconductor device when the input-signal pattern
12
is applied to the semiconductor device.
The pattern data memory
50
stores data of the input-signal pattern
12
and the expectation value signal pattern
14
. The sequence control unit
40
outputs an address signal
45
to the pattern data memory
50
so that the pattern data memory
50
generates the input-signal pattern
12
and the expectation value signal pattern
14
. The sequence control unit
40
receives a match signal
96
from the match signal generator
94
. The match signal
96
shows whether the output-signal pattern, which is output from the semiconductor device when the input-signal pattern
12
is applied to the semiconductor device, becomes the predetermined value that is determined based on the expectation value signal pattern
14
. The match-fail detecting unit
20
outputs a match-fail signal
22
to the sequence control unit
40
when the match-fail detecting unit
20
has not received a match signal
96
during a match cycle while waiting for the match signal
96
.
The sequence control unit
40
includes a pattern counter
42
, an address counter
44
, and a controller
46
. The pattern counter
42
counts match cycles. The address counter
44
counts addresses of control sequences. The controller
46
controls the pattern counter
42
and the address counter
44
according to the predetermined control sequence. The controller
46
also outputs a match cycle signal
43
to the match-fail detecting unit
20
. The match cycle signal informs the match-fail detecting unit
20
that the matching process is being processed. The controller
46
further outputs a clock control signal
48
to the reference clock generator
60
to stop generation of a clock signal when the controller
46
receives a match-fail signal
22
from the match-fail detecting unit
20
. The clock control signal
48
controls the reference clock generator
60
to stop generating a clock signal.
The controller
46
controls the pattern counter
42
and the address counter
44
in order to continue the control sequence when the controller
46
receives the match signal
96
during the match cycle. On the other hand, if the controller
46
receives the match-fail signal
22
, the controller
46
controls the pattern counter
42
and the address counter
44
in order to stop the control sequence, and the controller
46
executes a fail stop process that outputs the clock control signal
48
. The fail stop process stops a test. The test has to be started over again to restart the testing.
When a plurality of semiconductor devices are tested at the same time, a test is performed while confirming whether the writing of the input-signal pattern
12
to all the semiconductor devices and reading of the output-signal pattern from all the semiconductor devices have been finished normally. Thus, a series of tests are divided into several steps, and whether the reading and writing process of each semiconductor devices
200
has been finished is confirmed during a match cycle. The match cycle is a predetermined time period between each step of the series of tests. If the reading and writing process of each semiconductor device
200
has not been finished during the match cycle, it is found that there is a defective device within any one of a plurality of semiconductor devices. After the test is stopped, the defective device is removed from the test object, and then the test is restarted.
FIG. 2
is a flow chart that shows a process for testing one semiconductor device using a conventional semiconductor device testing apparatus. The input-signal pattern
12
is applied to a semiconductor device at test
1
(S
102
). Then, if the output-signal pattern output from the semiconductor device matches the predetermined value that is determined based on the expectation value signal pattern
14
during the match cycle (S
104
), a test
2
(S
106
) is performed continuously. However, if the output-signal pattern output from the semiconductor device does not match the predetermined value that is determined based on the expectation value signal pattern
14
during the match cycle (S
104
), the test finishes at that point as match-fail. Then, the same process is performed at a match cycle (S
108
) after the test
2
(S
106
). If the test
3
(S
110
) is finished, all the processes of testing have been finished.
FIG. 3
is a flow chart that shows a process for testing a plurality of semiconductor devices at the same time using a conventional semiconductor device testing apparatus. As shown in
FIG. 3
, if the output-signal pattern output from the semiconductor device matches the predetermined value during the match cycle (S
154
, yes) after the test
1
(S
152
) is performed, a test
2
(S
156
) is performed continuously.
However, if the output-signal pattern output from the semiconductor device does not match the predetermined value during the match cycle (S
154
, no) after the test
1
(S
152
) is performed, the test is stopped at that point as match-fail (S
162
). To test the other devices continuously after removing the semiconductor device that causes the match-fail from the test object after stopping the test (S
164
), the test
1
(S
152
) is performed again from the beginning. If the test does not continue, the test ends at that point.
After the test
2
(S
156
) has been performed, the same process using the process of the match cycle (S
154
) is performed at the match cycle (S
158
). If the output-signal pattern output from the semiconductor device does not match the predetermined value during the match cycle (S
158
, no) after the test
2
(S
156
) is performed, the test is stopped at that point as match-fail (S
162
). To test the other devices continuously after removing the semiconductor device that causes the match-fail from the test object after stopping the test (S
164
), the test
1
(S
152
) is performed again from the beginning. If the test does not continue, the test ends at that point. If the test
3
(S
160
) is finished, all the processes of the test end.
FIG. 4
is a time chart that shows a process for testing a plurality of semiconductor devices at the same time using a conventional semiconductor device testing apparatus. As shown in
FIG. 4
, a plurality of semiconductor devices are tested to see whether the output-signal pattern output from the semiconductor device matches the p
Advantest Corporation
Le John
Rosenthal & Osha L.L.P.
LandOfFree
Semiconductor device testing apparatus and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device testing apparatus and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device testing apparatus and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3117337