Semiconductor device testing apparatus

Details Semiconductor device testing apparatus Semiconductor device testing apparatus

2000-06-16

2002-05-07

Nguyen, Vinh P. (Department: 2858)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

C324S765010

Reexamination Certificate

active

06384593

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus suitable for testing one or more semiconductor devices, particularly one or more semiconductor integrated circuit elements (as will be referred to as IC or ICs hereinafter) which are typical examples of the semiconductor devices. More particularly, the present invention relates to a semiconductor device testing apparatus of the type in which ICs to be tested are transported, for testing, to a test or testing section where they are brought into electrical contact with a tester head (a component of the testing apparatus for applying and receiving various electrical signals for testing), followed by being carried out of the testing section and then being sorted out into conformable or pass articles and unconformable or failure articles on the basis of the test results.
2. Background of the Related Art
Many of the semiconductor device testing apparatuses (commonly called IC testers) for applying a test signal of a predetermined pattern to a semiconductor device to be tested, i.e. device under test (commonly called DUT) and measuring the electrical characteristics of the devices, have a semiconductor device transporting and handling or processing apparatus (commonly called handler) mounted or connected thereto. The handler which transports semiconductor devices to a testing section, brings them into electrical contact with a tester head in the testing section, and after the testing, carries the tested semiconductor devices out of the testing section, and sorts them out into pass articles and failure articles on the basis of the test results. In the specification, the testing apparatus which comprises a combination of the IC tester and the IC handler connected thereto or integrally mounted thereto of the type described above is termed “semiconductor device testing apparatus”. In the following disclosure the present invention will be described by taking ICs typical of semiconductor devices for example for clarity of explanation.
A description will be given first regarding the general construction of a conventional IC testing apparatus with reference to
FIGS. 4 and 5
.
FIG. 4
is a plan view of the IC testing apparatus schematically showing, in perspective, a chamber section
100
. In addition to the chamber section
100
, the illustrated IC testing apparatus further comprises an IC storage section
200
where ICs that will undergo a test (i.e., ICs to be tested) are stored and the tested ICs are sorted and stored in place, a loader section
300
where ICs to be tested which a user has beforehand loaded on a general-purpose tray (customer tray) KST are transferred and reloaded onto a test tray TST capable of withstanding high/low temperatures, and an unloader section
400
where the tested ICs which have been carried on the test tray TST out of the chamber section
100
subsequently to undergoing a test in the testing chamber
100
are transferred from the test tray TST to one or more general-purpose trays KST to be reloaded on the latter. The unloader section
400
is generally constructed to sort the tested ICs on the basis of the test results and load them on the corresponding general-purpose trays.
The chamber section
100
comprises a constant temperature or thermostatic chamber
101
for receiving the ICs to be tested loaded on the test tray TST and imposing an intended high or low temperature stress to the ICs, a test or testing chamber
102
for effecting an electrical test on the ICs subjected to the temperature stress in the constant temperature chamber
101
, and a temperature-stress removing chamber
103
for removing the temperature stress of the ICs having been applied thereto in the test chamber
102
from the ICs. The test chamber
102
contains therein a tester head
104
of the testing apparatus, supplies various electric signals for testing via the tester head
104
to the ICs to be tested in electrically contact therewith, receives response signals from the ICs, and sends them to the testing apparatus.
Each of the test trays TST is moved in a circulating manner from the loader section
300
through the constant temperature chamber
101
of the chamber section
100
, the test chamber
102
of the chamber section
100
, the temperature-stress removing chamber
103
of the chamber
100
, and the unloader section
400
in this order, to the loader section
300
. The constant temperature chamber
101
and the temperature-stress removing chamber
103
are taller than the chamber
102
, and have upward portions protruding beyond the top of the test chamber
102
, respectively. As shown in
FIG. 5
, a base plate
105
spans between the upward protruding portions of the constant temperature chamber
101
and the temperature-stress removing chamber
103
, and a test tray conveying means
108
is mounted on the base plate
105
to transport the test tray TST from the temperature-stress removing chamber
103
to the constant temperature chamber
101
.
In case the ICs to be tested have been heated to a high temperature (in this example, a thermal stress is applied to the ICs) in the constant temperature chamber
101
, the temperature-stress removing chamber
103
cools the tested ICs down to room temperature by blowing, after which they are transported to the unloader section
400
. On the other hand, in case the ICs to be tested have been cooled down or freezed to, for instance, −30° C. (in this example, a cryogenic stress is applied to the ICs) in the constant temperature chamber
101
, the temperature-stress removing chamber
103
heats the tested ICs by warm air or a heater up to a temperature at which the ICs have no any dew condensation, and then they are removed from the temperature-stress removing chamber
103
to the unloader section
400
.
The test tray TST with the ICs loaded thereon in the loader section
300
is conveyed from the loader section to the constant temperature chamber
101
within the chamber section
100
. The constant temperature chamber
101
has a vertical conveyor means mounted therein which is adapted to support a plurality of (nine, for instance) test trays TST in the form of a stack. In the illustrated example, the vertical conveyor means stacks the transported test trays such that a test tray newly received from the loader section
300
is supported at the uppermost of the stack while the bottom test tray is delivered to the test chamber
102
. The ICs to be tested on the uppermost test tray TST are given a predetermined high or low temperature stress while the associated test tray TST is moved sequentially from the top to the bottom of the stack by vertically downward movement of the vertical conveyor means and/or waits until the immediately preceding test tray is brought out of the test chamber
102
. The tester head
104
is disposed in the test chamber
102
at the central area thereof, and each of the test trays TST carried out one by one from the constant temperature chamber
101
is conveyed onto the tester head
104
while being maintained at the constant temperature, and a predetermined number of the ICs among the ICs on the associated test tray TST are electrically connected to IC sockets (not shown) mounted on the tester head
104
, as will be discussed hereinbelow. Upon completion of the test on all of the ICs placed on one test tray TST through the tester head
104
, the test tray TST is transported to the temperature-stress removing chamber
103
where the tested ICs on the associated test tray are relieved of heat to be restored to the ambient or room temperature, and thereafter the test tray TST is discharged to the unloader section
400
.
Like the constant temperature chamber
101
as described above, the temperature-stress removing chamber
103
is also equipped with a vertical conveyor means adapted to support a plurality of (nine, for instance) test trays TST stacked one on another. In the illustrated example, the test tray TST newly received from the test chamber
102
is supported at the

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