Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Patent
1997-05-28
2000-08-15
Nguyen, Vinh P.
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
324765, G01R 3128
Patent
active
061041831
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus suitable for testing one or more semiconductor devices, particularly one or more semiconductor integrated circuit elements (as will be referred to as IC or ICs hereinafter) which are typical examples of the semiconductor devices. More particularly, the present invention relates to a semiconductor device testing apparatus of the type in which ICs to be tested are transported, for testing, to a test or testing section where they are brought into electrical contact with a tester head (a component of the testing apparatus for applying and receiving various electrical signals for testing), followed by being carried out of the testing section and then being sorted out into conformable or pass articles and unconformable or failure articles on the basis of the test results.
2. Background of the Related Art
Many of the semiconductor device testing apparatuses (commonly called IC testers) for applying a test signal of a predetermined pattern to a semiconductor device to be tested, i.e. device under test (commonly called DUT) and measuring the electrical characteristics of the devices, have a semiconductor device transporting and handling or processing apparatus (commonly called handler) mounted or connected thereto. The handler which transports semiconductor devices to a testing section, brings them into electrical contact with a tester head in the testing section, and, after the testing, carries the tested semiconductor devices out of the testing section, and sorts them out into pass articles and failure articles on the basis of the test results. In the specification, the testing apparatus which comprises a combination of the IC tester and the IC handler connected thereto or integrally mounted thereto of the type described above is termed "semiconductor device testing apparatus". In the following disclosure the present invention will be described by taking ICs typical of semiconductor devices for example for clarity of explanation.
A description will be given first regarding the general construction of a conventional IC testing apparatus with reference to FIGS. 4 and 5. FIG. 4 is a plan view of the IC testing apparatus schematically showing, in perspective, a chamber section 100. In addition to the chamber section 100, the illustrated IC testing apparatus further comprises an IC storage section 200 where ICs that will undergo a test (i.e., ICs to be tested) are stored and the tested ICs are sorted and stored in place, a loader section 300 where ICs to be tested which a user has beforehand loaded on a general-purpose tray (customer tray) KST are transferred and reloaded onto a test tray TST capable of withstanding high/low temperatures, and an unloader section 400 where the tested ICs which have been carried on the test tray TST out of the chamber section 100 subsequently to undergoing a test in the testing chamber 100 are transferred from the test tray TST to one or more general-purpose trays KST to be reloaded on the latter. The unloader section 400 is generally constructed to sort the tested ICs on the basis of the test results and load them on the corresponding general-purpose trays.
The chamber section 100 comprises a constant temperature or thermostatic chamber 101 for receiving the ICs to be tested loaded on the test tray TST and imposing an intended high or low temperature stress to the ICs, a test or testing chamber 102 for effecting an electrical test on the ICs subjected to the temperature stress in the constant temperature chamber 101, and a temperature-stress removing chamber 103 for removing the temperature stress of the ICs having been applied thereto in the test chamber 102 from the ICs. The test chamber 102 contains therein a tester head 104 of the testing apparatus, supplies various electric signals for testing via the tester head 104 to the ICs to be tested in electrically contact therewith, receives response signals from the ICs, and sends them to the testing apparatus.
REFERENCES:
patent: 4103232 (1978-07-01), Sugita et al.
patent: 5150797 (1992-09-01), Shibata
patent: 5184068 (1993-02-01), Twigg et al.
patent: 5313156 (1994-05-01), Klug et al.
Ito Akihiko
Kobayashi Yoshihito
Masuo Yoshiyuki
Nakamura Hiroto
Nemoto Shin
Advantest Corporation
Nguyen Vinh P.
LandOfFree
Semiconductor device testing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device testing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device testing apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2010465