Semiconductor device testing apparatus

Details Semiconductor device testing apparatus Semiconductor device testing apparatus

1997-06-03

1999-06-01

Shah, Kamini

Data processing: measuring, calibrating, or testing

Testing system

G06F 1900

Patent

active

059096578

ABSTRACT:
A semiconductor device testing apparatus in which ICs to be tested are loaded on a test tray in a loader section, the test tray is transported into a test section to test the ICs, after the completion of the test, the tested ICs on the test tray are transferred from the test tray onto a general-purpose tray in an unloader section, the test tray which has been emptied of the tested ICs is transported to the loader section, and the above operation is repeated, and which can detect a failure of an IC carrier mounted to the test tray independently of detection of a failure IC socket is provided. An IC carrier failure analysis memory is provided which has storage addresses the number of which is equal to the number of IC carriers mounted to each of the test trays, and the number of ICs as determined to be defective is stored and accumulated in each of the storage addresses of the IC carrier failure analysis memory. When the accumulated value exceeds a setting value, a decision is rendered that the associated IC carrier on which the ICs as determined to be defective have been loaded is defective.

REFERENCES:
patent: 5715168 (1998-02-01), Ito
patent: 5772387 (1998-06-01), Nakamura et al.

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