Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
1998-12-15
2001-05-01
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S760020, C209S537000
Reexamination Certificate
active
06225798
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device testing apparatus (commonly called tester) for testing various types of semiconductor devices including semiconductor device integrated circuits (hereinafter each referred to as IC), and more particularly, to a semiconductor device testing apparatus of the type having a semiconductor device transporting and handling (processing) apparatus (commonly called handler) connected to the testing apparatus, for transporting various types of semiconductor devices to be tested (semiconductor devices under test, each commonly called DUT) to a testing or test station for testing them, and carrying the tested semiconductor devices out of the testing station for transport to a desired location.
BACKGROUND ART
Many of semiconductor device testing apparatuses for measuring the electrical characteristics of semiconductor devices to be tested, i.e. devices under test, by applying a test signal of a predetermined pattern to the devices have a semiconductor device transporting and handling (processing) apparatus (hereinafter referred to as handler) connected thereto for transporting semiconductor devices to a testing or test station where they are brought into electrical contact with sockets of the test head of the testing apparatus, followed by carrying the tested semiconductor devices out of the testing station and sorting them out into conforming (pass) and non-conforming (failure or defective) articles on the basis of the data of the test results.
In the following disclosure the electric or electronic part of the semiconductor device testing apparatus which measures the electrical characteristics of semiconductor devices under test by applying a test signal of a predetermined pattern to the devices is referred to as tester part, and a testing apparatus comprising the tester part and a handler or handlers connected to the tester part is referred to as semiconductor device testing apparatus (as will be referred to as tester hereinafter).
Generally, there are many cases that a tester comprising one tester part and two handlers connected to the tester part is operated as one tester. In such cases, the tester is arranged such that the two handlers are synchronously operated so that semiconductor devices in the two handlers can be tested at the same time. Also, there is often used a tester comprising one tester part and one handler which has two test stations provided therein and the two test stations are synchronously operated so that semiconductor devices in the two test stations can be tested at the same time.
In the following disclosure, for clarity of explanation, the present invention will be described by taking ICs typical of semiconductor devices as an example thereof.
First, one example of the testers of the type to which the present invention is intended to be applied will be described with reference to
FIGS. 5
to
7
.
FIG. 5
is a block diagram showing the general construction of an example of the IC tester comprising a tester part and a handler connected to the tester part in which the handler has two test stations provided therein which are synchronously operated so that ICs to be tested in the two test stations can be tested at the same time. This IC tester
100
comprises a tester part
1
including a tester proper
1
a
, a test or tester head
1
b
and an input part
1
c
, and a handler
2
connected to the tester part
1
.
The tester proper
1
a
includes an input/output interface circuit (hereinafter referred to as I/O circuit)
3
, and a central processing unit (hereinafter referred to as CPU)
4
, a read-only memory (hereinafter referred to as ROM)
5
and a random access memory (hereinafter referred to as RAM)
6
all of which are connected to the I/O circuit
3
. The test head
1
b
is separated from the tester proper
1
a
and is disposed at a first and a second test stations
15
a
and
15
b
of the handler
2
. The first and second test stations
15
a
and
15
b
will be discussed later. The CPU
4
reads out a system program stored in the ROM
5
therefrom to decode and process it, thereby to control the operations of the tester part
1
and the handler
2
.
The handler
2
comprises a loader section
16
where ICs to be tested which a user has beforehand loaded on universal trays or customer trays (hereinafter referred to as universal tray) are transferred and reloaded onto a test tray
14
capable of withstanding high/low temperatures, a chamber section for testing ICs under test
13
such as semiconductor memories which have been brought therein as loaded on a test tray
14
, and an unloader section
17
where the tested ICs which have been carried on the test tray
14
out of the chamber section subsequently to undergoing a test therein are transferred from the test tray
14
to the universal trays to be reloaded on the latter. The unloader section
17
is generally configured to sort out tested ICs based on the data of the test results and load them on the corresponding universal trays.
The chamber section comprises a constant temperature or thermostatic chamber (soak chamber)
12
a
for imposing temperature stresses of either a designed high or low temperature on ICs under test
13
loaded on a test tray
14
, a first and a second test chambers
12
b
and
12
c
for conducting a primary (first) measure and a secondary (second) measure on the ICs under the temperature stress imposed in the constant temperature chamber
12
a
respectively, and a temperature stress removing chamber (exit chamber)
12
d
for removing the temperature stress imposed in the constant temperature chamber
12
a
from the ICs having undergone the measures in the test chambers. The test chambers
12
b
and
12
c
are disposed in the constant temperature chamber
12
a
and contain thereunder the test head
1
b
of the tester part
1
, the two test stations
15
a
and
15
b
mounted on the test head
1
b
being disposed in the corresponding first and second test chambers
12
b
and
12
c
. The test stations
15
a
and
1
b
serve to apply various testing electrical signals to the ICs electrically contacted with the IC sockets thereof through the test head
1
b
, respectively, and to receive response signals from the ICs and transmit same to the tester part
1
.
The test tray
14
is moved in a circulating manner from and back to the loader section
16
sequentially through the constant temperature chamber
12
a
, the first test chamber
12
b
, the second test chamber
12
c
and the temperature stress removing chamber
12
d
of the chamber section, and the unloader section
17
.
If ICs have had a high temperature applied thereto in the constant temperature chamber
12
a
, the temperature stress removing chamber
12
d
cools the ICs with forced air down to the room temperature prior to delivering them out to the unloader section
17
. If ICs have had a low temperature of, say, about −30° C. applied thereto in the constant temperature chamber
12
a
, they are heated with heated air or a heater up to a temperature at which no condensation occurs prior to delivering them out to the unloader section
17
.
A test tray
14
, loaded with many ICs
13
to be tested in the loader section
16
, is conveyed from the loader section
16
to the constant temperature chamber
12
a
of the chamber section which is equipped with a vertical transport means in the temperature stress giving section therein adapted to support a plurality of (say, ten) test trays
14
in the form of a stack. For example, a test tray newly received from the loader section
16
is supported on the top of the stack while the lowermost test tray is delivered out to the first test chamber
12
b.
ICs
13
to be tested are loaded with either a predetermined high or low temperature stress as the associated test tray
14
is moved sequentially from the top to the bottom of the stack by the vertically downward movement of the vertical transport means and during a waiting period until the first test chamber
12
b
is emptied. In the first test chamber
12
b
and the s
Onishi Takeshi
Suzuki Katuhiko
Advantest Corporation
Gallagher & Lathrop
Lathrop David N.
Metjahic Safet
Nguyen Jimmy
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