Data processing: measuring – calibrating – or testing – Testing system – Including multiple test instruments
Reexamination Certificate
2001-04-26
2003-04-15
Barlow, Jr., John E. (Department: 2863)
Data processing: measuring, calibrating, or testing
Testing system
Including multiple test instruments
C324S1540PB, C714S721000
Reexamination Certificate
active
06549868
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device test system and a semiconductor device test method for specifying a leakage portion on the wiring of a semiconductor device such as an LSI (large scale integrated circuit). The present invention particularly relates to a semiconductor device test system and a semiconductor device test method for specifying a leakage portion on a semiconductor device by applying a current and a magnetic field to the semiconductor device and detecting a stress generated thereby.
2. Description of the Related Art
Recently, semiconductor devices tend to be very small in size and highly integrated. Due to this, if a leak current occurs to a wiring in a semiconductor device, it becomes more difficult to specify a leakage portion.
Now, by way of example, a conventional test system and a conventional test method for specifying the leakage portion of a semiconductor device will be shown. The test system and the test method specify a portion to which a leak current occurs by detecting a magnetic field generated by the leak current.
FIG. 1
is a block diagram showing the constitution of this test system. A stage
54
is provided in a testing section
50
. A semiconductor device
55
to be tested is mounted on the stage
54
. A microscope
51
for observing the wiring pattern of the semiconductor device
55
, an image detector
52
for converting an image obtained by the microscope
51
into an electrical signal and a light source
53
for illuminating the semiconductor device
55
are arranged above the stage
54
and the semiconductor device
55
. Also, a magnetic field measuring terminal
58
for detecting a magnetic field generated from the semiconductor device
55
is provided in the testing section
50
.
Meanwhile, a power supply
57
for allowing current to flow the semiconductor device
55
is provided outside of the testing section
50
. There is also provided a position controller
62
into which the detection signal of the image detector
52
is inputted, for moving the microscope
51
, the image detector
52
and the light source
53
based on this detection signal and controlling their positions. Further, a signal outputted from the magnetic field detection terminal
58
is inputted into a magnetic field detector
59
. Besides, there is provided a control computer
60
for controlling the position controller
62
, the magnetic field detector
59
, the light source
53
and the stage
54
. The input and output signals of the control computer
60
are inputted into and outputted from each of the position controller
62
, the magnetic field detector
59
, the light source
53
and the stage
54
. There is further provided an image processor
63
for recognizing and processing, as images, the wiring pattern of the semiconductor device
55
obtained by the image detector
52
and a magnetic field detection result about the semiconductor device
55
obtained by the magnetic field detector
59
. A signal outputted from the control computer
60
is inputted into the image processor
63
. The output signal of the image processor
63
is inputted into an image display unit
64
and displayed thereon as an image. An instruction signal is inputted into the control computer
60
by an input unit
61
.
Next, a semiconductor device test method using the test system shown in
FIG. 1
will be described.
FIG. 2
is a flow chart showing procedures for this test method. First, as shown in a step S
401
of
FIG. 2
, a defective semiconductor device
55
is mounted on the stage
54
shown in FIG.
1
. Next, as shown in a step S
402
, instructions for controlling the positions of the microscope
51
, the image detector
52
and the light source
53
and the position and inclination of the stage
54
are inputted into the control computer
60
by the input unit
61
. The input signal is outputted from the control computer
60
and inputted into the position controller
62
to control the positions of the microscope
51
, the image detector
52
and the light source
53
. In addition, this input signal is inputted into the stage
54
to control the position and inclination of the stage
54
. Thereafter, using the microscope
51
, the wiring pattern of the semiconductor device
55
illuminated by the light source
53
is observed and a wiring pattern image is picked up. Next, the image detector
52
converts the pattern image obtained by the microscope
51
into an electrical signal. Then, the image detector
52
outputs the electrical signal to the image processor
63
through the control computer
60
. The image processor
63
recognizes the pattern image as an image and outputs the pattern image to the image display unit
64
. The image display unit
64
displays the pattern image. Thereafter, as shown in a step S
403
, the image processor
63
records this pattern image data.
Then, as shown in a step S
404
, a current is inputted from the power supply
57
into the wiring of the semiconductor device
55
to turn the semiconductor device
55
into a defective operation state. As shown in a step S
405
, the magnetic field measuring terminal
58
detects a magnetic field generated on the wiring of the semiconductor device
55
. Next, as shown in a step S
406
, the magnetic field measuring terminal
58
converts the detected magnetic field into an electrical signal and feeds the electrical signal to the magnetic field detector
59
. The magnetic field detector
58
processes the electrical signal and outputs the resultant electrical signal to the image processor
63
through the control computer
60
. The image processor
63
creates a magnetic field image based on this output signal and feeds the created image to the image display unit
64
. The image display unit
64
displays the magnetic field image. Then, as shown in a step S
407
, the image processor
63
records the magnetic field image. As shown in a step S
408
, the image processor
63
creates a synthetic image by superposing the magnetic field image on the previously recorded pattern image. Then, as shown in a step S
409
, the image display unit
64
displays this superposed image. Next, as shown in a step S
410
, the data analysis of this synthetic image is performed to thereby specify a leakage portion.
Furthermore, as another conventional test method, Japanese Patent Unexamined Application Publication No. 6-314726 discloses a method of applying a magnetic field in perpendicular direction to the wiring of a defective semiconductor device while voltage is being applied to the device, irradiating the wiring with primary electrons and detecting secondary electrons. According to this method, it is possible to measure a leak current value from the potential difference in the width direction of the wiring.
The above-stated conventional techniques have, however, the following disadvantages. According to the method of detecting a magnetic field generated by a leak current, a magnetic field derived from a leak current and that derived from a normal current are included in detected magnetic fields. Due to this, the magnetic field generated by the leak current is often cancelled depending on the manner in which the normal current flows, with the result that a leakage portion cannot be disadvantageously specified.
Furthermore, according to the method disclosed by Japanese Patent Unexamined Application Publication No. 6-314726, if a leakage portion is covered with another wiring, primary electrons do not reach the leakage portion and the leakage portion cannot be, therefore, disadvantageously specified.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device test system and a semiconductor device test method capable of showing a leak current while separating the leak current from a normal current and accurately specifying a leakage portion even if the leakage portion is covered with another wiring.
A semiconductor device test system for specifying a portion of a semiconductor device in which leak current occurs, co
Barlow Jr. John E.
Le John
NEC Corporation
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