Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-06-02
2001-08-28
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090
Reexamination Certificate
active
06281693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device test board and a method for testing a semiconductor device, and more particularly relates to a semiconductor device test board and a method for testing a semiconductor device used for testing a semiconductor device having solder bumps.
2. Description of the Related Art
Recently, semiconductor devices have achieved higher density, higher speed and a multi-pin structure. Along with the above improvements, semiconductor devices using solder bumps as external connection terminals came into use.
The above described semiconductor device is subjected to various tests such as a burn-in test with the solder bumps connected to a semiconductor device test board. Accordingly, to provide a semiconductor device with high reliability, there is a need for a positive connection between the semiconductor device and the semiconductor device test board. Also, when removing the semiconductor device from the test board, it is required not to damage the solder bumps.
FIGS. 1-3
show a semiconductor device test board and a method for testing a semiconductor device according to the related art.
A semiconductor device test board
10
A, shown in
FIG. 1
, includes a supporting board
12
made of an insulating material such as glass or ceramics, a metal pattern
14
formed on the supporting board
12
, contact parts
20
A, and an insulating layer
22
. The contact parts
20
A will be connected to solder bumps
18
provided on a semiconductor device
16
to be tested. The insulating layer
22
is provided on the metal pattern
14
avoiding locations where the contact parts
20
A are formed.
The contact parts
20
A are provided at openings formed on the insulating layer
22
. Each contact part
20
A is formed of an upper layer
26
and a lower layer
24
. In the related art, the lower layer
24
is formed of nickel (Ni), and the upper layer
26
formed of gold (Au).
Accordingly, as shown in
FIG. 1
, when the semiconductor device
16
is mounted on the semiconductor device test board
10
A, the solder bumps
18
are connected by fusion on the upper layers
26
of the contact parts
20
A. Predetermined reliability tests such as a burn-in test are carried out in such a connected state.
Generally, copper (Cu) is used for forming a wiring pattern of the board. Accordingly, the lower layer
24
is formed of nickel in order to provide an improved adhesiveness with copper (Cu) and to act as a barrier to gold forming the upper layer
26
. Also, the upper layer
26
is formed of gold (Au) in order to provide an improved adhesiveness with the solder bump
18
and to prevent an oxidization of a surface of the nickel layer
24
.
In the following, the solder bumps
18
on the semiconductor device
16
will be described in detail. There are two types of solder bumps. One is a solder bump
18
which acts as an input/output for signals and electrical power when testing the semiconductor device (in the following, referred to as a testing solder bump
18
a
). The other type is a solder bump
18
which is not used when testing the semiconductor device (in the following, referred to as a non-testing solder bump
18
b
).
The testing solder bump
18
a
is connected to the contact part
20
A as described above, whereas there is no contact part
20
A formed at the position of the non-testing solder bump. Therefore, when testing the semiconductor device, the non-testing solder bump directly touches the insulating layer
22
.
FIGS. 2 and 3
show an example of a semiconductor device test board
10
B which uses a dome-shaped solder pad
28
as a contact part
20
B. In
FIGS. 2 and 3
, the same elements as those of the semiconductor device test board
10
A of
FIG. 1
are shown with the same reference numbers.
When the semiconductor device test board
10
B is used, the semiconductor device
16
is mounted on the semiconductor device test board
10
B by direct fusion connection of the solder pad
28
to the solder bump
18
provided on the semiconductor device
16
. In this connected state, predetermined reliability tests such as the burn-in test are carried out.
However, when the semiconductor device test board
10
A is used (see FIG.
1
), there is a problem that the solder bump
18
is degraded by a heating process carried out during the test, thereby decreasing the reliability of the semiconductor device
16
. This will be described in detail later.
When the semiconductor device test board
10
A shown in
FIG. 1
is used, the solder bumps
18
are connected to the upper layer
26
formed of gold (Au). Because of the heat history of the heating process carried out in the testing step, a gold-tin (Au—Sn) alloy is formed. During the re-forming of the solder bumps
18
caused by a re-flow step which is performed after the testing step, the Au—Sn alloy is mixed into the solder bumps
18
. Therefore, there was a problem of a degradation of the solder bumps and a decrease in the reliability of the semiconductor device
16
.
In the case of the semiconductor device test board
10
B shown in
FIGS. 2 and 3
, when the semiconductor device
16
is mounted on the semiconductor device test board
10
B and the solder bump
18
is connected with the solder pad
28
, the solder forming this solder pad
28
escapes or protrudes from the side (see the central part of FIG.
2
). In the following, this solder is referred to as escape solder
29
.
As shown in
FIG. 2
, when the solder escapes, the escape solder
29
will be placed on top of the insulating layer
22
. This prevents the solder bump
18
and the metal pattern
14
from being electrically connected. Therefore there is a problem that a proper test of the semiconductor device
16
cannot be carried out.
Also, both the solder bump
18
and the solder pad
28
have considerably good bonding ability since they are formed of solder. Therefore, their bonding strength will be stronger when they are connected by fusion. Accordingly, when removing the semiconductor device
16
from the semiconductor device test board
10
B after the test, there may be a case that the bonding strength of the solder bump
18
is greater against the semiconductor device test board
10
B than against the semiconductor device
16
.
In the above case, as shown in
FIG. 3
, the solder bump
18
may peel off from the semiconductor device
16
and remain on the semiconductor device test board
10
B (the solder bump shown on the left part of FIG.
3
). This created a problem that the semiconductor device
16
may be damaged by performing a test thereon.
Also, in the related art, the non-testing solder bump
18
b
directly touches the insulating layer
22
during the test. Therefore, when the semiconductor device
16
is mounted on the semiconductor device test board
10
A,
10
B, the distance between the semiconductor device
16
and the semiconductor device test board
10
A,
10
B is limited by the height of the non-testing solder bump
18
b
. This causes a problem that the testing solder bump
18
a
and the contact part
20
A,
20
B will not connect easily (referred to as a spring-back phenomenon).
Further, in the related art, the supporting board
12
is formed of glass and ceramics, which are relatively expensive. This leads to a problem of high production cost of the semiconductor device test board
10
A,
10
B. In order to reduce the cost of the semiconductor device test board
10
A,
10
B, a glass/epoxy board is preferably used as a supporting board
12
. However, the glass/epoxy board may not be used in the related art because of its greater thermal expansion compared to that of a board made of either glass or ceramics. This causes a greater amount of the escape solder
29
shown in
FIGS. 2 and 3
to be produced. Therefore there is a problem in that the glass/epoxy board may not be used.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a semiconductor device test board and a method of testing a semiconductor device, which can solve the above problems.
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Karlsen Ernest
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