Semiconductor device test arrangement with reassignable...

Details Semiconductor device test arrangement with reassignable... Semiconductor device test arrangement with reassignable...

2006-02-14

2006-02-14

Patel, Paresh (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C324S1540PB

Reexamination Certificate

active

06998865

ABSTRACT:
A test arrangement includes a semiconductor device, a first conductive pad electrically connected to the semiconductor device, a second conductive pad, and a programmable fuse. The second conductive pad is electrically connected to the semiconductor device through the programmable fuse.

REFERENCES:
patent: 4064493 (1977-12-01), Davis
patent: 4152627 (1979-05-01), Priel et al.
patent: 4853628 (1989-08-01), Gouldsberry et al.
patent: 4862243 (1989-08-01), Welch et al.
patent: 5202624 (1993-04-01), Gheewala
patent: 5708291 (1998-01-01), Bohr et al.
patent: 5898312 (1999-04-01), Uhling et al.
patent: 5898700 (1999-04-01), Kim
patent: 5973504 (1999-10-01), Chong
patent: 5982188 (1999-11-01), Lysinger
patent: 6060899 (2000-05-01), Hamada
patent: 6104082 (2000-08-01), Berlin et al.
patent: 6175145 (2001-01-01), Lee et al.
patent: 6214630 (2001-04-01), Hsuan et al.
patent: 6255835 (2001-07-01), Oh et al.
patent: 6277674 (2001-08-01), Wang et al.
patent: 6346820 (2002-02-01), Yamagami
patent: 6368902 (2002-04-01), Kothandaraman et al.
patent: 6433404 (2002-08-01), Iyer et al.
patent: 6506634 (2003-01-01), Kohyama
patent: 6710640 (2004-03-01), Kothandaraman et al.
patent: 661552 (1995-07-01), None
patent: 1122784 (2002-08-01), None
patent: WO0193331 (2001-12-01), None
NN76091161 “IBM technical Disclosure Bulletin” Sep. 1976, US.
Klee, et al., “A 0.13 um logic-based embedded DRAM technology with electrical fuses, Cu interconnect in SiLK, sub-7ns random access time and its extension to the 0.10 um generation.”, Technical Digest, International Electron Device Meeting 2001, Washington, D.C., Dec. 2-5, 2001, pp. 407-411, (Four Pages).
IBM Technical Disclosure Bulletin, vol. 37, No. 12, Dec. 1994, p. 617, “Release Interface Tape Programmable Probe Pad”. (One Page).

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