Semiconductor device such as a static random access memory (SRAM

Details Semiconductor device such as a static random access memory (SRAM Semiconductor device such as a static random access memory (SRAM

1997-06-12

1998-12-08

Mai, Son

Static information storage and retrieval

Powering

Conservation of power

365233, G11C 514

Patent

active

058480145

ABSTRACT:
An internal clock signal disable circuit is disclosed for disabling an internal clock signal used in a synchronous static random access memory (SRAM). The reduced power mode is preferably a sleep mode commanded by assertion of a reduced power command signal, which may be a Jedec-standard "ZZ" signal. The disable circuit includes a pair of latch devices clocked by clock signals deriving from the external clock signal applied to the SRAM. The ZZ signal is applied to the input of the first latch, whose output is connected to the input of the second latch. The output of the second latch is processed to generate disable signals for disabling generation of the internal clock signal used on the device. The pair of latches insures that a delay is introduced prior to disabling the internal clock so that at least one clock pulse of the internal clock signal is generated before the internal clock is shut down. The ZZ signal is also applied to chip enable input buffers, which cause such buffers to output a signal as if a non-active chip enable signal was actually applied to the device. The non-active chip enable signals thus output from the input buffers are captured by respective chip enable registers by the above-mentioned at least one further clock pulse. Through the foregoing, no external deselection of the device need be made prior to asserting the reduced power command signal (i.e., "ZZ").

REFERENCES:
patent: 5247164 (1993-09-01), Takahashi
patent: 5247655 (1993-09-01), Khan et al.
patent: 5337285 (1994-08-01), Ware et al.
patent: 5430393 (1995-07-01), Shankar et al.
patent: 5452434 (1995-09-01), MacDonald
patent: 5563839 (1996-10-01), Herdt et al.

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