Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2000-06-19
2002-02-12
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S059000, C257S072000, C257S350000
Reexamination Certificate
active
06346717
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, a substrate for an electro-optical device, the electro-optical device, an electronic equipment, and a projector.
2. Description of Related Art
The SOI (Silicon On Insulator) technology in which a semiconductor device is formed on a silicon insulator film on top of an insulating substrate has been extensively studied because the SOI technologies offer high-speed, low-power consumption features and the high degree of integration in devices.
One of the SOI technologies is a manufacturing technique of an SOI substrate in which monocrystalline silicon substrates are laminated. In this method, called a lamination technique, after a monocrystalline silicon substrate and a support substrate are laminated using hydrogen bond force, the strength of the lamination is reinforced by a thermal treatment, and the monocrystalline silicon substrate is subjected to grinding and abrasion or a thin-film monocrystalline silicon layer is formed on the support substrate using etching technique. Since this technique directly constructs a thin-film monocrystalline silicon substrate, a resulting silicon thin film has an excellent crystallinity, leading to the manufacture of a high-performance device.
Known techniques developed from the lamination method include one technique (U.S. Pat. No. 5,374,564) in which hydrogen ions are implanted into a monocrystalline silicon substrate to be laminated onto a support substrate, and the thin-film silicon layer is separated from the hydrogen implanted region of the monocrystalline silicon substrate through a heat treatment; and another technique (Japanese Unexamined Patent Publication No. 4-346418) in which a monocrystalline silicon layer is epitaxially grown on a silicon substrate having a porous surface, the resulting substrate is laminated on a support substrate, the silicon substrate is then removed, and the porous silicon layer is then etched away so that the epitaxial thin layer of monocrystalline silicon is thus formed on the support substrate.
Like ordinary bulk semiconductor substrates, the SOI substrate manufactured in accordance with the lamination method finds widespread use in a variety of devices, but one of the differences from the conventional bulk substrates is that various materials may be used as a support substrate. As a support substrate, not only ordinary silicon substrate, but also transparent quartz substrate or glass substrate may be used. By forming a monocrystalline silicon thin film on a transparent substrate, a device that needs light transmissivity, such as a transmissive liquid-crystal display device, is manufactured, and a high-performance transistor device using a monocrystalline silicon having an excellent crystallinity is thus provided.
In the field-effect transistor on an ordinary silicon substrate, or so-called MOSFET (Metal Oxide Semiconductor Field Effect Transistor), by fixing a well potential, a channel potential of the MOSFET formed in the same well is fixed. In the SOI substrate, however, the substrate surface on which the channel region of the MOSFET is formed is an insulator, and the channel regions are electrically completely isolated from transistor to transistor, and the potential of each channel needs to be fixed on a per transistor basis. If the channel potential remains unfixed, the channel region is subject to carrier (charge) accumulation because of the effect of a floating substrate. Particularly when the channel region is constructed of a monocrystalline silicon, the charge mobility is high in the monocrystalline silicon, and a charge accumulates in the channel region because of a potential difference between the source and drain when the MOSFET is turned off. When the MOSFET is turned on, an excess current tends to flow. In the thin-film structure of the MOSFET, a diversity of problems arise, for example, an excess carrier (charge) lowers the breakdown voltage of the drain of the transistor element or causes a kink in the current-voltage characteristics of the transistor element. The fixing of the channel potential is thus required.
Known methods for fixing the channel potential using an excess charge include one technique called a source tie (IEEE Trans. Eelectron Device, Vol. 35, p. 1391, 1988) in which a channel and a source are equalized in potential by forming a conductive impurity zone in the source region identical to a channel in semiconductor type, and another technique called H(T) type gate (IEEE Trans. Electron Device, Vol. ED-36, p. 938, 1989, for example) in which a contact is formed on a channel region extending from the end of a gate.
SUMMARY OF THE INVENTION
Depending on the potential applied, the source and the drain alternate in a MOSFET which is arranged for each pixel in a liquid-crystal panel and which supplies each pixel with a voltage in response to a signal, and a symmetrical property is thus required of the MOSFET. To allow the MOSFET produced on the SOI substrate to drive the liquid crystal, the source tie structure that has an asymmetrical MOSFET structure cannot be used. To employ a fairly symmetrical H(T) type gate, a potential line for fixing the channel potential is required in addition to scanning lines and data lines. The transmissive liquid-crystal display device in which a lightness is important suffers a drop in the aperture ratio.
It is an object of the present invention to provide a semiconductor device which is made highly reliable and excellent in quality by fixing a channel potential of a MOSFET to a light shielding layer that shields the MOSFET from a light ray in a semiconductor device of the MOSFET formed on an insulator such as an SOI substrate, and to provide highly reliable and excellent quality substrate for electro-optical device, electro-optical device employing the substrate, electronic equipment employing the electro-optical device, and projector.
DISCLOSURE OF THE INVENTION
The semiconductor device of the present invention, having a semiconductor layer formed on an insulator, includes a transistor in which at least a channel region is formed in the semiconductor layer, and a light shielding layer for shielding the transistor from a light ray, wherein the light shielding layer is electrically connected to the channel region of the transistor. In accordance with the present invention, the light shielding layer shields the transistor from a light ray, preventing the transistor from erratically operating due to a leakage current arising from light and thereby stabilizing the potential of the channel. Since the voltage is applied to the channel of the transistor, the effect of a floating substrate is thus controlled by draining an excess carrier (charge) accumulated in the channel to the light shielding layer. The withstanding voltage of the transistor is thus improved, and kinks in the current-voltage characteristics of the transistor are controlled.
In the present invention, preferably, the transistor is an N-channel-type transistor, and the light shielding layer electrically connected to the channel region of the N-channel-type transistor is supplied with a low power source potential. In the N-channel-type transistor, the charge is accumulated in its channel region. By supplying the low power source potential, the excess carrier (charge) is efficiently drained and the potential of the channel is thus stabilized.
In the present invention, preferably, the transistor is an N-channel-type transistor, and the light shielding layer electrically connected to the channel region of the N-channel-type transistor is supplied with a potential equal to or lower than the lowest potential of the potential applied to one of the source and the drain of the N-channel-type transistor. The carrier (charge) is efficiently drained by supplying the low power source potential equal to or lower than the lowest potential of the potential applied to one of the source and the drain of the N-channel-type transistor.
In the present invention, preferably, the transistor is a P-ch
Ngo Ngan V.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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