Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2000-06-22
2002-09-17
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
Reexamination Certificate
active
06452284
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to semiconductor devices and, more particularly, alignment features used for aligning a semiconductor device substrate.
RELATED ART
In semiconductor manufacture, it is often important in process steps to accurately align the semiconductor device before performing an operation. For example, accurate alignment is important in laser fusing and laser annealing. Such process steps are typically employed in repair, hard coding of logic, and other steps.
In order to accurately align the semiconductor device, laser optics are conventionally employed and alignment aids or features formed for such purpose. The alignment aids or features can include various geometric configurations, such, as substantially L-shaped or T-shaped marks or slots. A low-power, continuous wave laser beam is passed in two directions over the alignment aid. In the alignment process, the optics detect laser reflections at high and low intensity levels, and the laser tool is positioned consistent therewith. The continuous wave laser energy and the optics detect a center point of the alignment aid or mark and adjustment of laser position is made to correspond with the center point detection. Typically, at least one other alignment aid at a different location is analyzed in a similar manner to establish reference points for moving to desired positions on the semiconductor wafer for laser fusing or annealing.
Alignment structures may take a variety of different forms.
FIG. 1
includes a conventional alignment aid, which is identified as alignment structure
100
. The alignment structure
100
is formed from an uppermost conductor
110
of a semiconductor device. The uppermost conductor
110
overlies a plurality of oxide layers
120
, each of which is not a reflective layer. In this particular alignment configuration, the alignment structure
100
includes an alignment key
112
, in this instance an L-shaped slot in the uppermost conductor
110
. In an alignment operation, the laser beam is reflected as it passes across the uppermost conductor
10
, but reflection is significantly less when the laser beam passes across the plurality of oxide layers
120
.
U.S. Pat. No. 5,311,061, issued May 10, 1994, entitled “Alignment Key for a Semiconductor Device Having a Seal Against Ionic Contamination” discloses a type of alignment structure in a semiconductor substrate that, in essence, forms a box. Referring to FIG. 4—4 of that patent, the box is fabricated to prevent diffusion of mobile ionic contaminants through the alignment key into other portions of the semiconductor substrate. Typically, the structure is somewhat larger than the alignment feature. However, an area around the structure may be exposed to the laser beam during aligning. If floating gate memory cells lie too close to the alignment structure during alignment, a programmed memory cell may be disturbed. Therefore, an area having approximately 200 microns (&mgr;m) per side surrounds the center point of the structure. No electrical components are placed within that area, and therefore, a significant amount of substrate area is wasted as unusable for location of electronic components.
REFERENCES:
patent: 5311061 (1994-05-01), Sheck
patent: 5701013 (1997-12-01), Hsia et al.
patent: 5760483 (1998-06-01), Bruce et al.
patent: 6081040 (2000-06-01), Okuda et al.
patent: 6157087 (2000-12-01), Zhao et al.
patent: 04-13349 (1992-05-01), None
Meyer George R.
Motorola Inc.
Rodriguez Robert A.
Weiss Howard
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