Semiconductor device structure which provides individually contr

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

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257347, 257372, H01L 2941

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active

058083464

ABSTRACT:
An N-type well region (NW) is provided on a P-type bulk silicon substrate (PS), and a channel region (PC) is provided inside the N-type well region (NW). The channel region is formed of a semiconductor layer having a polarity opposite to that of a source region (ST) and a drain region (DT). A contact hole (CHC) is provided in a gate oxide film (GO) located below a main portion (MP) close to an end portion (EP) of a gate electrode (GT). With this construction, a semiconductor device in which a body terminal is connected to a gate terminal for fast operation can remove restriction on location for connecting the body terminal and the gate terminal to achieve size-reduction and overcome disadvantages due to restriction on supply voltage.

REFERENCES:
patent: 5014109 (1991-05-01), Higuchi
patent: 5498882 (1996-03-01), Houston
patent: 5559368 (1996-09-01), Hu et al.
patent: 5619072 (1997-04-01), Mehta
1994 IEEE, IEDM, pp. 809-812, 1994, Fariborz Assaderaghi, et al., "A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation".
1996 IEEE International Solid-State Circuits Conference, pp. 84-85, 1996, Takakuni Douseki, et al., "A 0.5V Simox-MTCMOS Circuit With 200ps Logic Gate".
1995 IEEE International Solid-State Circuits Conference, pp. 88-89, 1996, Tsuneaki Fuse, et al., "0.5V SOI CMOS Pass-Gate Logic".

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