Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
2002-06-13
2004-11-30
Bradley, P. Austin (Department: 2833)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C439S266000, C439S330000
Reexamination Certificate
active
06824395
ABSTRACT:
This application is based on Patent Application No. 2001-180576 filed Jun. 14, 2001 in Japan, the content of which is incorporated hereinto by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device-socket used for testing the semiconductor device.
2. Description of the Related Art
Semiconductor devices mounted on an electronic equipment or others are subjected to various tests at a stage prior to being actually mounted so that latent defects therein are removed. The test is performed nondestructively under conditions such as application of voltage stress, high-temperature operation, and high-temperature storage, corresponding to thermal and mechanical environment tests or the like.
A semiconductor device-socket made available for such tests comprises, as illustrated in FIG.
7
and
FIG. 8
for example, a base
2
disposed on a printed circuit board
4
that includes an input/output section through which a predetermined inspection signal is inputted and outputted, an object under test-accommodation member
6
, which is disposed on the base
2
for accommodating a semiconductor device
12
as a specimen to be inspected, and a plurality of contact terminals
10
ai
(i=1 to n, n is a positive integer) each for electric connection between each lead of the semiconductor device
12
accommodated in the object under test-accommodation member
6
and each electrode of the printed circuit board
4
, as the main components.
The base
2
includes mounting holes
2
a
in four places into each of which a screw is inserted. Screws are used to fix the base section
2
onto the printed circuit board
4
. The base
2
includes openings
2
b
provided in four places in the center of itself, into each of which openings each of pawls
6
A,
6
B,
6
C, and
6
D of the object under test-accommodation member
6
described later is inserted. Around a peripheral edge of each opening
2
b
a pawl
2
N is provided, which is engaged with the foregoing pawls
6
A,
6
B,
6
C, and
6
D.
A thin sheet-shaped contact terminal
10
ai
comprises a board-side terminal fixed to the electrode of the printed circuit board
4
, a contact portion in contact with each lead of the semiconductor device
12
described later, and a curved coupling section for coupling the board-side terminal to the contact portion. The contact terminals
10
ai
on each line are disposed oppositely to each other, across the object under test-accommodation member
6
at a predetermined mutual distance. Further, the contact terminals
10
ai
are arranged longitudinally of the object under test-accommodation member
6
. The board-side terminal is fixed to the inside of the base
2
, and contact portions of the board-side, on the other hand, are inserted into and engaged with a groove in the object under test-accommodation member
6
described later.
The object under test-accommodation member
6
includes the four pawls
6
A to
6
B at its lower end corresponding to the opening
2
b
. The pawls
6
A to
6
B are protruded toward the inside of the opening
2
b
. Between the object under test-accommodation member
6
and the base
2
are provided coiled springs
8
A and
8
B each for supporting the object under test-accommodation member
6
.
The object under test-accommodation member
6
includes at the center thereof a accommodating section
14
in which the semiconductor device
12
is accommodated. The accommodating section
14
is surrounded by an inclined guide surface
14
s
, a bottom surface
14
b
that forms the bottom of the accommodating section
14
, and each upright surface
14
f
that intersects with the guide surface
14
s
and the bottom surface
14
b.
In a portion of an outer peripheral section of the accommodating section
14
of the object under test-accommodation member
6
opposing the contact terminals
10
ai
on each line is formed a slit
6
gi
(i=1 to n, n is a positive integer, with which the contact portions of the contact terminals
10
ai
are engaged. The slit
6
gi
is formed between adjacent partition walls at a predetermined interval therebetween.
In such a construction, when the semiconductor device
12
is tested, the semiconductor device
12
held by a conveying robot (not shown) is disposed in place directly over the accommodating section
14
of the object under test-accommodation member
6
, and is thereafter dropped down from a predetermined height and is mounted on the accommodating section
14
as indicated by a chain double-dashed line in FIG.
8
. Each lead of the semiconductor device
12
is thus placed on the contact portion of each contact terminal
10
ai.
Referring here to
FIG. 9
for example, when the semiconductor device
12
is dropped down in a slanting position from a predetermined height in error for some reason, the end portion of the semiconductor device
12
is guided to the guide surface
14
s
of the accommodating section
14
, and simultaneously the lead
12
c
of the semiconductor device
12
is made to slide on the upper surface of the partition wall and on the contact portions of the contact terminals
10
ai,
and thereafter the semiconductor device
12
is positioned in place.
However, as illustrated in
FIG. 9
, when the semiconductor device
12
is dropped in a slanting position, the lead
12
c
of the semiconductor device
12
is caught on a step Da in size as small as about several tens of micrometers between the contact portion surface
10
s
of the contact portion of the contact terminal
10
ai
and an upper surface of the partition wall between the adjacent slits
6
gi.
As a consequence, the semiconductor device
12
may no longer be positioned in place within the accommodating section
14
.
In such a situation, since it may be contemplated that such a step Da happens on the basis of the manufacturing error involving assembling error, and hence it is reasonable to take measures to reduce the manufacturing error to a minimum so that a surface formed by the contact surface
10
s
of the contact portion of the contact terminal
10
ai
and the upper surface of the partition wall between the adjacent slits
6
gi
are flush with each other. However, this causes increasing manufacturing costs, and as the position of the contact portion surface
10
s
of the contact portion of the contact terminal
10
ai
is varied vertically, it is not easy to limit the size of the step Da within several tens of micrometers, in actual fact, that is close to impossible.
SUMMARY OF THE INVENTION
In view of the aforementioned problems with the prior art, it is an object of the present invention to provide a semiconductor device-socket for use in a test on the semiconductor device, wherein it is capable of securely guiding a lead of the semiconductor device to be mounted in place in a contact portion of a contact terminal when the semiconductor device is mounted.
To achieve the above object, according to an aspect of the present invention, there is provided a semiconductor device-socket comprising: a plurality of slits each of which is formed around a semiconductor device accommodating section in which the semiconductor device including a plurality of leads are accommodated, corresponding to an array of the leads, the slit engaged with contact terminals including the contact portions electrically connected with the leads respectively; and a plurality of partition walls formed around the semiconductor device accommodating section as to continue on the plurality of the slits and dividing the adjacent slits, wherein at least the one partition wall among the foregoing plurality of the partition walls has a slope that connects the uppermost end located at a higher position than the position of a contact portion of a first contact terminal among the contact terminals and the lowest end located at a lowest position than the position of the contact portion of a second contact terminal adjacent to the first contact terminal.
According to an aspect of the present invention, there is provided a semiconductor device-socket comprising:
Bradley P. Austin
Finnegan Henderson Farabow Garrett & Dunner LLP
Leon Edwin A.
Yamaichi Electronics Co. Ltd.
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