Semiconductor device silicon via fill formed in multiple dielect

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257741, 257751, 257774, 437189, 437190, 437161, H01L 2934, H01L 2348, H01L 2946, H01L 21225

Patent

active

052910580

ABSTRACT:
A semiconductor device with an electrode wiring structure comprises at least one diffused region provided in a semiconductor substrate, a silicon oxide layer covering the substrate surface, a silicon nitride layer provided on the silicon oxide layer, a through-hole reaching the diffused region through the silicon oxide layer from an upper surface of the silicon nitride layer, a silicon semiconductor layer filled in the through-hole and serving as an electrode wiring layer, and an interconnection layer electrically connected to the diffused region through the silicon semiconductor layer. According to the structure, since the silicon oxide layer is covered with the silicon nitride layer, unwanted contaminations such as phosphorus, boron, etc., previously contained in the silicon oxide layer are not added to the silicon semiconductor layer during its growth process. Therefore, the electrode wiring layer of silicon semiconductor having controlled conductivity can be provided.

REFERENCES:
patent: 4576834 (1986-03-01), Sobczak
patent: 4843033 (1989-06-01), Plumton et al.
patent: 4884123 (1989-11-01), Dixit et al.
patent: 5072276 (1991-12-01), Malhi et al.
patent: 5116780 (1992-05-01), Samata et al.
Mieno et al., "Novel Selective Poly- and Epitaxial-Silicon Growth (SPEG) Technique for ULSI Processing," IEDM, pp. 16-19 (1987).
Shibata et al., "Low-Resistive and Selective Silicon Growth as a Self-Aligned Contact Hole Filler and its Application to 1M bit Static RAM," Technical Digest for 1987 Symposium on VLSI Technology, pp. 75-76 (1984).
Tanno et al., "Selective Silicon Epitaxy Using Reduced Pressure Technique," Japanese Journal of Applied Physics, vol. 21, No. 9, pp. L564-L566 (1982).
Wolf et al., Silicon Processing for the VLSI Era, vol. 1: Process Technology, pp. 182-191 (1986).
Ogawa et al., "The Selective Epitaxial Growth of Silicon by Using Silicon Nitride Film as a Mask," Japanese Journal of Applied Physics, vol. 10, No. 12, pp. 1675-1679 (1971).
Borland, "Novel Device Structures by Selective Epitaxial Growth (SEG)", IEDM, pp. 12-15 (Dec. 6-9, 1987).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device silicon via fill formed in multiple dielect does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device silicon via fill formed in multiple dielect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device silicon via fill formed in multiple dielect will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-580264

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.