Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-10-05
2003-09-09
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S118000, C438S123000, C257S678000, C257S780000
Reexamination Certificate
active
06617193
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to a substrate for mounting semiconductor elements (called semiconductor device substrate hereafter), a semiconductor device in which the semiconductor elements are mounted on the semiconductor device substrate and methods of fabricating them.
2. Related Art
There is growing needs for a smaller semiconductor device package with multiple terminal pins due to increases of an integration rate and an operation frequency in the recent semiconductor device. However, a package size of a conventional peripheral terminal type utilizing a leadframe has to be made larger if a number of the terminals should be increased further. One of countermeasures is to decrease a terminal pitch in the package. However, it is difficult to make the terminal pitch narrower than 0.4 mm.
To accommodate such increasing number of the terminals, an area array type package with its terminals disposing over a surface plane is introduced. The area array type package requires to have a wiring substrate for providing wiring from a pad of semiconductor chips to external connection terminals. The semiconductor chip may be mounted either at the upper surface or the lower surface of the wiring substrate when the external connection terminals are disposed at the lower surface of the wiring substrate. When the semiconductor chip is mounted on the upper surface of the wiring substrate, interlayer connections between the upper surface and the lower surface of the wiring substrate have to be provided. When the semiconductor chip is mounted on the lower surface of the wiring substrate, the interlayer connections will not be required. However, a hollow space has to be provided to absorb total thickness of the semiconductor chip and its sealing material when the semiconductor chip is mounted on the lower surface of the wiring substrate.
The hollow space is called a cavity, and a structure with the cavity at the lower surface of the wiring substrate is called a cavity down structure. Typically, the structure can be made by hollowing out a semiconductor chip substrate, or by making a hole through the semiconductor device substrate and adhering a base plate thereto. Wiring for a multiple layer structure is required when heights of semiconductor chip bonding portions and external connection terminals are changed because the wiring is also disposed on the same surface in this structure. That is, a wiring structure body in consideration of a three dimensional spatial relationships among the semiconductor chip mount portion, the inner bonding portion connected to mounted semiconductor chips and the external connection terminal portion in which external connection terminals are formed.
One of the area array type semiconductor package is Ball Grid Array (BGA) in which solder balls are used as external connection terminals. Cost of the BGA is higher than that of a semiconductor device fabricated with a conventional leadframe, and reduction of the cost is anticipated. The higher cost is due to a fact that a structure and fabricating process of the semiconductor device substrate are more complex than that of a substrate with the leadframe. Accordingly, it is anticipated the development of simpler structure and fabricating process of the semiconductor device substrate.
The wiring substrate used for the area array type semiconductor package is typically called an interposer. The interposer may be roughly classified into a film type and a rigid plate type. A number of the wiring layers can be either one, or two, or three and more layers. Generally, the fabricating cost is lower for a fewer number of the wiring layers.
In the interposer so called TAB (Tape Automated Bonding) or TCP (Tape Carrier Package) and their packaging technology, the center portion of the interposer is bored through to store the semiconductor chip. With the rigid plate, the center portion of the interposer is similarly bored through to hollow the semiconductor chip store portion out and adhere a metal plate as a base plate thereto, or the cavity portion is fabricated at the center area of the interposer. The wiring is disposed only in a flat plane portion, not inside the cavity portion.
SUMMARY OF THE INVENTION
Among those conventional technologies, the lowest cost is expected with the single layer wiring structure. If the wiring is disposed at least in both surfaces of the interposer, the semiconductor chip mount portion and the external connection terminals may be divided at the upper and the lower surfaces.
However, the semiconductor chip mount portion and the external connection terminals are disposed on the same surface of the interposer with the single layer wiring structure. In such a single layer wiring structure, it is required to have the cavity portion on the wiring surface with a depth at least comparable to a thickness of the chip so as to store the chip therein. A method of fabricating such a cavity portion has become an important subject.
Further, recently, smaller external connection terminals such as solder balls have been promoted and the reduction of its height when mounted and the realization of finer pitches for external connection terminals have been attempted. However, in order to obtain thinner and smaller semiconductor devices, the structure optimization is also an important issue for the structure such as the semiconductor chip mount portion and the wiring substrate in consideration of technical developments of those smaller external connection terminals.
The present invention is made by considering the above mentioned subjects. An object of the present invention is to provide a semiconductor device substrate for mounting a semiconductor chip(s) and other elements, a method of fabricating the semiconductor device substrate, a semiconductor device wherein a semiconductor chip(s) is mounted on the semiconductor device substrate, and a method of fabricating the semiconductor device, those of which enable to reduce the size, increase the reliability, reduce the cost, and make standardization of design and fabricating method easier.
Another object of the present invention is to provide a semiconductor device, a semiconductor device substrate therefor and methods of fabricating them, which allow reduction of the thickness and the size of the semiconductor device.
Still another object of the present invention is to provide a semiconductor device substrate having a cavity portion and a semiconductor device using the same, the cavity portion having a structure determined based on the size of external connection terminals to be used.
The above object of the present invention is accomplished by a semiconductor device substrate with a cavity portion, or a semiconductor device fabricated by mounting at least one semiconductor chip in the cavity portion and sealing with sealant, wherein said semiconductor device substrate comprises wiring disposed along a surface of the substrate and wall surfaces of the substrate in the cavity portion, the wiring comprises an external connection terminal portion for connecting to external connection terminals which are provided on the surface of the substrate at a side of the cavity portion being opened, an internal connection terminal portion for connecting to the mounted semiconductor chip, and a wiring portion disposed in between the external connection terminal portion and the internal connection terminal portion, the wiring portion is buried in a surface of the substrate and one of said wall surfaces of the substrate in the cavity portion and the internal connection terminal portion is disposed inside of the cavity portion.
For example, the wall surface of the substrate in the cavity portion may be extended toward the bottom surface of the cavity portion with a slant angle which is set within a predetermined angle range. Concretely, the slant angle may be within a range of 5-40°, and preferably within a range of 10-40°. In other words, the slant structure may be fabricated so as that a ratio L/G may be within ranges of 1.2<L/G<11,
Akinari Kida
Hiroshi Morita
Kazuhisa Suzuki
Naoki Fukutomi
Susumu Naoyuki
Hitachi Chemical Company Ltd.
Lebentritt Michael S.
Luu Pho
Pennie & Edmonds LLP
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