Semiconductor device, semiconductor device pattern designing...

Details Semiconductor device, semiconductor device pattern designing... Semiconductor device, semiconductor device pattern designing...

2000-04-25

2004-01-20

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C438S926000

Reexamination Certificate

active

06680539

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, a semiconductor device pattern designing method, and a semiconductor device pattern designing apparatus. More particularly, the invention relates to a semiconductor device suitably structured to minimize wiring layer step differences thereof, as well as to a method and an apparatus for designing semiconductor device patterns suitable for minimizing their wiring layer step differences.
2. Description of the Background Art
FIG. 8
is a cross-sectional view of a conventional semiconductor device
10
. The semiconductor device
10
is an eRAM (embedded device) that has a logic circuit and a DRAM (dynamic random access memory) mounted on a single substrate which is a silicon substrate
12
. The silicon substrate
12
has an isolation oxide film
14
embedded therein, the film
14
having been formed by a shallow-trench process.
Formed on the silicon substrate
12
are gate electrodes
16
and side walls
18
which are components of the logic circuit, and transfer gates (TG)
20
and side walls
22
which are components of the DRAM. A first interlayer film
24
made of BPSG is formed on the gate electrodes
16
and transfer gates
20
. The first interlayer film
24
has multiple contact plugs
26
conducting to active regions of the DRAM.
The contact plugs
26
are formed as follows: contact holes
28
to be opened in the active regions of the DRAM are first formed in the first interlayer film
24
. Doped polysilicon is then deposited to fill the inside of the contact holes
28
. Lastly, CMP (chemical mechanical polishing) is carried out to flatten the top of the first interlayer film
24
and the edges of the contact plugs
26
.
A second interlayer film
30
made of TEOS is formed on the first interlayer film
24
. The semiconductor device
10
includes bit lines
32
and metal wiring
34
, the bit lines
32
penetrating the second interlayer film
30
to conduct to some of the contact plugs
26
, the metal wiring
34
penetrating the first and second interlayer films
24
and
30
to conduct to the active regions of the logic circuit. The bit lines
32
and metal wiring
34
are formed as follows: contact holes
36
penetrating the second interlayer film
24
and contact holes
38
penetrating the first and second interlayer films
24
and
30
are formed first. Tungsten silicide (WSi) is then deposited all over the second interlayer film
30
to fill the inside of the contact holes
36
and
38
. Lastly, the tungsten silicide (WSi) is patterned to desired shapes by photolithography and etching.
A third interlayer
40
made of TEOS is formed on the second interlayer film
30
. The semiconductor device
10
has storage node contact plugs (SC plugs)
42
that penetrate the second and third interlayer films
30
and
40
to conduct to some of the contact plugs
28
. The SC plugs
42
are formed as follows: contact holes
44
penetrating the second and third interlayer films
30
and
40
are first formed. Doped polysilicon is then deposited to fill the inside of the contact holes
44
. Lastly, CMP is performed to flatten the top of the third interlayer film
40
and the edges of the SC plugs
42
.
A fourth interlayer film
46
made of BPSG is formed on the third interlayer film
40
. The fourth interlayer film
46
has openings
48
that lead to the SC plugs
42
. The inner walls of the openings
48
and the surfaces of the SC plugs
42
are covered with an insulating film
50
. A cell plate
52
made of doped polysilicon is formed to fill inside voids enclosed by the insulating film
50
and cover the fourth interlayer film
46
. The cell plate
52
is formed as follows: openings
48
penetrating the fourth interlayer film
46
are first formed. The insulating film
50
is formed so as to cover inside the openings
48
. Doped polysilicon is then deposited all over the fourth interlayer film
46
to fill the inside of the openings
48
. Lastly, the doped polysilicon is patterned to desired shapes by photolithography and etching.
On an eRAM such as the semiconductor device
10
, the cell plate
52
is formed only in the DRAM area. Once the cell plate
52
is formed, its film thickness tends to cause a step difference in elevation between the DRAM area and the logic circuit area.
A fifth interlayer film
54
is formed on the fourth interlayer film
46
so as to cover the cell plate
52
. The semiconductor device
10
has multiple metal wires
56
conducting to the cell plate
52
and to the metal wiring
34
. The metal wires
56
are formed as follows: openings are first made in the fifth interlayer film
54
and fourth interlayer film
46
. Then barrier metal (e.g., TiN: 15 nm) and wiring material (e.g., AlCu: 150 nm) are deposited all over the fifth interlayer film
54
to fill these openings. Lastly, the deposited films are patterned to desired shapes by photolithography and etching. The above processes are repeated as many times as needed to form a multiple-layer wiring structure.
An eRAM such as the semiconductor device
10
has a pattern like the cell plate
52
that exists only in one of the DRAM and the logic circuit. The presence of such a pattern leads to a step difference at the pattern top between the DRAM area and the logic circuit area. The step difference formation tends to reduce margins for photolithography and is liable to produce faulty contact hole openings or to degrade wiring pattern precision. The CMP process intended to reduce the step difference can result in an irregular polish because of the bumpy surface to be polished.
SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to overcome the above and other disadvantages of the prior art and to provide a semiconductor device having dummy patterns for ensuring the flatness of wiring layers.
It is a second object of the present invention to provide a pattern designing method for designing wiring patterns which include dummy patterns suitable for ensuring the flatness of wiring layers.
It is a third object of the present invention to provide a pattern designing apparatus for designing wiring patterns by use of the above-mentioned inventive pattern designing method.
The above objects of the present invention are achieved by a semiconductor device having a multi-layer wiring structure. The device includes functional patterns necessary for implementing functions of the semiconductor device. The device also includes dummy patterns formed together with the functional patterns in selected layers. The dummy patterns are constituted by a plurality of patterns having different sizes.
The above objects of the present invention are also achieved by a semiconductor device pattern designing method for designing patterns of a semiconductor device having a multi-layer wiring structure. The method includes pattern designing processes each provided for individual layer included in the multi-layer wiring structure. In each of the pattern designing processes, functional patterns are designed for implementing functions of the semiconductor device, then a plurality of types of dummy patterns are designed so as to have different sizes in free regions not occupied by the functional patterns. For designing the dummy patterns, the first and second sub-steps described below are repeatedly performed. In the first sub-step, dummy patterns of a predetermined size are laid-out as many as possible in the free regions. In the second sub-step, the predetermined size of the dummy patterns is made smaller.
The above objects of the present invention are further achieved by a semiconductor device pattern generating apparatus for designing patterns of a semiconductor device having a multi-layer wiring structure. The apparatus includes pattern designing unit each provided for individual layer included in the multi-layer wiring structure. Each of the pattern designing unit has a functional pattern designing unit for designing functional patterns necessary for implementing functions of the semiconductor device as well

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