Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-03-29
2004-10-12
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230030, C365S230060
Reexamination Certificate
active
06804161
ABSTRACT:
Japanese Patent Application No. 2001-103416, filed on Apr. 2, 2001, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device which retains data by refreshing, a method of refreshing this semiconductor device, a memory system, and an electronic instrument.
A virtually static RAM (VSRAM) is one type of semiconductor memory. Although memory cells of a VSRAM are the same as memory cells of a DRAM, the VSRAM does not need multiplexing of the column and row addresses. Moreover, the user can use the VSRAM without taking refreshing into consideration (transparency of refreshing).
BRIEF SUMMARY OF THE INVENTION
The present invention may provide a semiconductor device which retains data by refreshing, a method of refreshing this semiconductor device, a memory system, and an electronic instrument.
(1) A method of refreshing a semiconductor device in accordance with one aspect of the present invention relates to a method of refreshing a semiconductor device having a memory cell array divided into a plurality of blocks, the method comprising:
an external access step of reading or writing data continuously with respect to a block selected from the plurality of blocks, by generating a plurality of addresses continuously by a pulse signal, based on one address specified by an address signal;
a detection signal generation step of generating a detection signal having a period longer than the pulse signal and detecting a change in the address signal; and
a refreshing step of refreshing blocks in the plurality of blocks other than the selected block, based on the detection signal.
The external access step refers to the generation of a plurality of sequential addresses, such as first to fourth addresses, based on a specification by a first address, and the execution of continuous data read or write with respect to the memory cells of those addresses. The external access step entails an extreme shortening of the period of the pulse signal, because of reading or writing data at high speed, and a shortening of the period in which refreshing is done. For that reason, if references to the external access and refreshing are set on this pulse signal, it could happen that a block to be externally accessed is being refreshed, delaying the external access. This aspect of the present invention makes it possible to perform external access and refreshing with reference to the above-described detection signal that has a period longer than that of the pulse signal, thus preventing any delay in external access.
This aspect of the present invention also makes it possible to refresh the other blocks while the block selected by address is being externally accessed, enabling efficient operation of the semiconductor device.
The generation of a plurality of addresses by the pulse signal, based on one address specified by the address signals, refers to the generation of a plurality of column addresses in sequence by the clock signal, based on one column address, by way of example. In this case, the row address is the same.
The detection signal contains an address transition detector (ATD) signal, by way of example.
The pulse signal contains a clock signal or a signal that is multiplied from the clock signal within the semiconductor device, by way of example.
An address signal that is input from the outside to the semiconductor device could be used unchanged as the address signal, by way of example. In addition, the address signal from the outside could be converted into a block address signal, a column address signal, and a row address signal, where those signals could be used as an address signal.
The number of blocks selected by address for external access could be one or more. The number of blocks that are to be accessed externally can be arbitrarily determined depending on the design of the semiconductor device.
Refreshing with respect to a block means the refreshing of memory cells in a certain row in a block. A “row” could be one row or it could be a plurality of rows. This can be determined arbitrarily, based on the design of the semiconductor device.
External access means a read of data from a memory cell or a write of data thereto, by way of example.
(2) In this method of refreshing a semiconductor device, the refreshing step may comprise:
a refresh request step of generating a refresh request with respect to each of the plurality of blocks, based on the detection signal; and
a refresh execution step of refreshing blocks in the plurality of blocks other than the selected block, based on the refresh request.
(3) In this method of refreshing a semiconductor device,
the refresh execution step may end in a period between the generation of the detection signal and the generation of the next detection signal.
This ensures that when an attempt is made to access a certain block externally, that block is not being refreshed and thus external access is not delayed.
A semiconductor device in accordance with another aspect of the present invention comprises:
a memory cell array divided into a plurality of blocks;
a pulse signal generation circuit which generates a pulse signal;
a detection signal circuit which generates a detection signal having a period longer than the pulse signal and detecting a change in an address signal;
an address generation circuit which generates a plurality of addresses sequentially by the pulse signal, based on the one address specified by the address signal, so as to perform continuous reading or writing of data with respect to a block selected from the plurality of blocks; and
a refresh circuit which refreshes blocks in the plurality of blocks other than the selected block, based on the detection signal.
This aspect of the present invention is similar to that described in (1).
(5) In this semiconductor device, the address generation circuit may comprise a column address generation circuit to which a column address signal out of the address signal is input, and which generates a plurality of column addresses by the pulse signal, based on the column address signal.
(6) In this semiconductor device, the refresh circuit may comprise:
a plurality of refresh request signal generation circuits each provided corresponding to each of the plurality of blocks, which generate refresh request signals with respect to the plurality of blocks, based on the detection signal; and
a plurality of block controllers each provided corresponding to each of the plurality of blocks,
wherein one of the plurality of block controllers, which corresponds to the selected block, may generate an external access execution signal with respect to the selected block; and
wherein remaining block controllers, which correspond to the blocks other than the selected block, may generate refresh execution signals based on the refresh request signals.
(7) A memory system in accordance with further aspect of the present invention may comprise any of the semiconductor devices described in (4) to (6) above.
(8) An electronic instrument in accordance with still another aspect of the present invention may comprise the memory system described in (7) above.
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Nelms David
Nguyen Thinh T
Oliff & Berridg,e PLC
Seiko Epson Corporation
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