Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
1997-07-28
2001-07-24
Parker, Kenneth (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S147000, C257S763000, C257S770000
Reexamination Certificate
active
06266110
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having at least two metal layers and having metals provided not only in wiring regions but regions other than the wiring regions, and to a reflection type liquid crystal display. Particularly, the present invention relates to a semiconductor device suitable for use in a semiconductor chip for driving a reflection type liquid crystal arranged on the semiconductor chip, such as a silicon (Si) chip based liquid crystal, having a surface on which light is incident and capable of preventing the incident light from reaching a substrate transistor within the device and from causing the device to malfunction, and to a semiconductor device for driving reflection type liquid crystal using the semiconductor device.
2. Description of the Related Art
If light is incident on a transistor, current flows due to, for example, recombination. Such unexpected current causes malfunction of a semiconductor device. To solve this, a semiconductor device is usually incorporated within a light shielding package. However, there exists a semiconductor chip wherein light is incident on a chip surface such as a semiconductor device for driving a reflection type liquid crystal.
In such a semiconductor chip, conventionally, metals are provided not only in wiring regions but also in regions other than wiring regions to shield light as shown in FIG.
17
. In
FIG. 17
, reference numeral
10
denotes a semiconductor substrate made of, for example, silicon (Si), reference numeral
12
denotes a diffused layer region for a source and drain formed in a well in the semiconductor substrate
10
, reference numeral
14
denotes a LOCOS (Local Oxidation of Silicon) for electrically separating elements, reference numeral
16
denotes a first interlayer insulating film formed on the semiconductor substrate
10
including the diffused layer region
12
and the LOCOS
14
, reference numeral
18
denotes a polysilicon (p-Si) gate which is a conductor formed in the first interlayer insulating film
16
, reference numeral
20
denotes a first metal wiring layer communicated with either the diffused layer region
12
or the polysilicon gate
18
by a contact hole
17
at necessary position, reference numeral
22
denotes a second interlayer insulating film formed on the first metal wiring layer
20
, reference numeral
24
denotes a second metal wiring layer formed on the second interlayer insulating film
22
, reference numeral
26
denotes a third interlayer insulating film formed on the second metal wiring layer, reference numeral
28
denotes a third metal wiring layer formed on the third interlayer insulating film
26
and communicated with the second metal wiring layer
24
through a via hole
30
and reference numeral
32
denotes a space within the third metal wiring layer
28
.
In this semiconductor chip, for purposes of preventing transmission of incident light, a metal (usually such as aluminum-silicon alloy Al—Si) is provided not only in wiring regions but in regions other than the wiring regions to form a dummy wiring which is used as a light shielding portion in the second metal wiring layer
24
and the third metal wiring layer
28
.
However, the following problems occur to such a semiconductor chip as the incident light increases.
That is, if light is incident on the semiconductor chip, there is a possibility that the incident light passes two passages I
1
and I
2
shown in FIG.
17
and reaches the diffused layer region
12
of a substrate transistor.
As regards passage I
1
, the uppermost (or third) metal wiring layer
28
in the via hole
30
is thinner than the flat portion of the layer
28
in terms of metal coverage. Due to this, the incident light transmits the via hole
30
of the uppermost metal wiring layer
28
and reaches the substrate transistor while repeating irregular reflection.
As regards passage I
2
, the incident light transmits the space
32
where no metal is present within the uppermost metal wiring layer
28
and reaches the substrate transistor while repeating irregular reflection on the metal surface as in the case of I
1
.
The light, which has transmitted the uppermost metal wiring layer
28
through the via hole
30
and the space
32
, cannot directly reach the substrate transistor due to the presence of the light shielding portion. However, repeating reflection on the metal surface having large reflectivity, the incident light reaches indirectly the substrate transistor.
In addition, according to the conventional semiconductor device as shown in
FIG. 18
where a MOS transistor is illustrated, a plurality of diffused layer regions
12
serving as a source and a drain are provided on a semiconductor substrate
10
and a first metal wiring layer
20
made of such as aluminum is provided to connect the elements through a contact hole
17
between respective diffused layer regions
12
. The configuration of metal wiring layers varies with element arrangement. In
FIG. 18
, a lower wiring layer by a polysilicon gate
18
and the like is provided.
In such a case, as is well known, the flatness of the interlayer films with respect to the lower wiring layer depends on the wiring width or wiring spacing, especially the latter, of the polysilicon gate
18
serving as a lower wiring layer. Therefore, if various wiring spacings exist in the semiconductor chip, conditions or method of forming interlayer films disadvantageously becomes complex.
To solve this, as shown in
FIG. 19
, electrically independent dummy wirings
21
are provided in a wide wiring spacing. By forming the dummy wiring
21
, wiring spacing can be narrowed and conditions and method of forming interlayer films can be thereby made simpler than in the case where no dummy wiring is provided.
However, the conventional method of forming normal wiring
20
and independent dummy wiring
21
has a problem that the dummy wiring
21
cannot be inserted if the spacing between the normal wirings
20
is not wider than the allowable minimum spacing between wirings for providing the dummy wiring of minimum width.
In other words, as shown in
FIG. 20
, if the spacing between normal wiring
20
is greater than 2S+L (where S is a minimum wiring spacing allowed by the wiring rule and L is a minimum wiring width allowed by the wiring rule), it is possible to insert a dummy wiring
21
having a width of L+&agr; greater than L. On the other hand, if the spacing between the wiring
20
is smaller than 2S+L, the width of the dummy wiring
21
is L−&agr; smaller than a minimum wiring width L as shown in FIG.
21
. This is out of the design rule and eventually the dummy wiring
21
is eliminated and cannot be left.
As mentioned above, the flatness of an interlayer film between wiring layers depend on a wiring spacing. As shown in
FIG. 22
, for example, a coating film
34
by a normal SOG (Spin On Glass) is put between CVD (Chemical Vapor Deposition) oxide films
36
as an interlayer film between a polysilicon gate
18
, which is a lower wiring layer, and a wiring layer
20
. In such a case, there exists an optimum wiring spacing for flattening the interlayer film by burying the coating film
34
into a recessed part. However, there is a problem that if a wiring spacing into which a dummy wiring cannot be inserted, the interlayer film cannot be sufficiently flattened.
Furthermore, as the high integration of an LSI (Large Scale Integrated circuit) progresses, wiring become narrower and multiple wiring layers are increasingly formed. To realize narrow wiring and multiple wiring layers, it is necessary to maintain an enough focus depth when a resist pattern is exposed to light during the step of patterning wiring by reticle. As a result, it becomes increasingly important to sufficiently flatten layers.
As a method of realizing flat layers, a so-called CMP (Chemical Mechanical Polishing) method is widely known. The CMP method is for polishing and flattening uneven portions of an oxide film formed on a wiring.
The CMP method
Fujishima Masaaki
Hanihara Koji
Iwahashi Masanori
Mizuno Makoto
Shimizu Toshihiro
Kawasaki Steel Corporation
Oliff & Berridg,e PLC
Parker Kenneth
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