Semiconductor device, receiver circuit, and frequency...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S159000, C327S161000

Reexamination Certificate

active

07098711

ABSTRACT:
A delay circuit is provided including: 2n(n is a natural number) unit delay circuits for delaying an input clock signal (with the period of T) in accordance with a delay setting signal and generating and outputting 2nphases of delayed clock signals; a phase locked circuit for locking phases of the input clock signal and an output clock signal of a predetermined one of the unit delay circuits so as to be in phase and for outputting the delay amount setting signal for causing each of the first to the last stages of the unit delay circuits to delay the phase of an output clock signal by T/2n; and a correction circuit to which the input clock signal and the delay amount setting signal are input for generating a corrected clock signal by delaying the input clock signal and outputting it to the delay circuit.

REFERENCES:
patent: 4358741 (1982-11-01), Nardin
patent: 5712884 (1998-01-01), Jeong
patent: 6259294 (2001-07-01), Murakami et al.
patent: 6417706 (2002-07-01), Kondo
patent: 6737901 (2004-05-01), Hein et al.
patent: 6788119 (2004-09-01), Hyland et al.
patent: 2003/0080783 (2003-05-01), Kozaki
patent: 2002-232490 (2002-08-01), None
patent: 2003-124787 (2003-04-01), None

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