Active solid-state devices (e.g. – transistors – solid-state diode – Transmission line lead
Reexamination Certificate
2001-11-14
2003-07-15
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Transmission line lead
C327S111000, C327S536000
Reexamination Certificate
active
06593642
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly a semiconductor device provided with a potential transmission line for transmitting an internal potential to a plurality of load capacitors.
2. Description of the Background Art
FIG. 15
is a circuit block diagram showing a major portion of a Dynamic Random Access Memory, which will be referred to as a “DRAM” hereinafter, in the prior art. In
FIG. 15
, the DRAM includes a memory array MA, a detector circuit
50
, a ring oscillator
51
and a charge pump circuit
52
. Memory array MA includes a plurality of memory blocks MB arranged in rows and columns (10 rows and 7 columns in FIG.
15
).
Memory block MB includes, as shown in
FIG. 16
, a plurality of memory cells MC arranged in rows and columns, word lines WL arranged corresponding to the respective memory cell rows, and bit line pairs BL and /BL arranged corresponding to the respective memory cell columns. Each memory cell MC includes an N-channel MOS transistor
53
and a capacitor
54
. N-channel MOS transistor
53
is connected between corresponding bit line BL or /BL and a storage node SN, and has a gate connected to corresponding word line WL. Capacitor
54
is connected between storage node SN and a line bearing a cell plate potential.
In a write operation, word line WL in the row corresponding to the row address signal is raised to a boosted potential VPP sufficiently higher than a power supply potential VCC, and N-channel MOS transistor
53
of memory cell MC, which is connected to the above word line WL, is turned on. Then, bit line pair BL and /BL in the column corresponding to the column address signal is selected, and one bit line (e.g., BL) in selected bit line pair BL and /BL is set to power supply potential VCC in accordance with write data signal. The other bit line (e.g., /BL) is set to ground potential GND. Thereby, the potential on bit line BL or /BL is written onto storage node SN of memory cell MC.
In a read operation, each bit line pair BL and /BL is set to a bit line precharge potential VBL equal to VCC/2, and then word line WL on the row corresponding to the row address signal is raised to boosted potential VPP. Thereby, N-channel MOS transistor
53
of memory cell MC connected to word line WL is turned on, and a minute potential difference occurs between paired bit lines BL and /BL in accordance with the potential on storage node SN of memory cell MC. The minute potential difference between paired bit lines BL and /BL is amplified to the power supply voltage by a sense amplifier (not shown). Then, bit line pair BL and /BL on the column corresponding to the column address signal is selected, and a comparison is made between the potentials on the paired bit lines BL and /B. Thereby, data of a logic corresponding to the result of this comparison is externally output as read data of selected memory cell MC. As described above, word line WL designated by the row address signal is raised to boosted potential VPP. This is performed for the purpose of sufficiently writing power supply potential VCC onto storage node SN of memory cell MC, and sufficiently reading out power supply potential VCC on storage node SN.
FIG. 17
is a cross section schematically showing a structure of memory block MB. In
FIG. 17
, an N-type bottom well
56
is formed at a surface of a P-type semiconductor substrate
55
. Further, P-type well
57
is formed at the surface of N-type bottom well
56
. N-channel MOS transistor
53
of memory cell MC is provided with a gate electrode
53
g
, which is formed on the surface of P-type well
57
with a gate insulating film (not shown) therebetween, and an N-type diffusion layer located on the opposite sides of gate electrode
53
g
and formed at the surface of P-type well
57
. The N-type diffusion layers on the opposite sides of gate electrode
53
g
form a source
53
s
and a drain
53
d
of N-channel MOS transistor
53
, respectively.
P-type semiconductor substrate
55
, N-type bottom well
56
and P-type well
57
are supplied with ground potential GND, boosted potential VPP and negative potential VBB for applying a reverse bias voltage to a PM junction, respectively. Parasitic capacitors C
3
and C
4
occur between N-type bottom well
56
and P-type semiconductor substrate
55
and between N-type bottom well
56
and P-type semiconductor substrate
55
, respectively.
Referring to
FIG. 15
, seven power supply lines PL are arranged corresponding to seven columns of memory blocks MB, respectively. One end of each of seven power supply lines PL is connected to corresponding one of seven output nodes of charge pump circuit
52
. Each power supply line PL extends across and above ten memory blocks MB, and applies boosted potential VPP to N-type bottom wells
56
of corresponding memory blocks MB. A bottom well capacitor C
1
is present between power supply line PL and each memory block MB. Bottom well capacity C
1
includes parasitic capacitors C
3
and C
4
shown in FIG.
17
.
Power supply lines PL′ are arranged between ten rows of memory blocks MB as well as on the opposite sides of the whole area including the ten rows. Power supply lines PL and PL′ are connected together at crossing portions between them. Each output node of charge pump circuit
52
is connected to a decouple capacitor C
2
. Decouple capacitor C
2
is provided for preventing a rapid change in potential VPP on power supply lines PL and PL′. A potential detecting line DL, which has an end connected to detector circuit
50
, is disposed between charge pump circuit
52
and memory array MA, and extends across seven power supply lines PL. Potential detecting line DL is connected to the respective power supply lines PL at the crossings between them. Potential detecting line DL has a much lower resistance value than power supply lines PL and PL′. Therefore, potential VPP on a base end (node NA) of power supply line PL is accurately transmitted to detector circuit
50
.
Detector circuit
50
determines whether boosted potential VPP has reached a predetermined reference potential VR or not. If boosted potential VPP has not yet reached reference potential VR, detector circuit
50
sets a signal LOW to “H” level, which is an active level. If boosted potential VPP has reached reference potential VR, detector circuit
50
sets signal LOW to “L” level, which is an inactive level. Detector circuit
50
quickly responds to a change in level of boosted potential VPP for rapidly supplying charges when boosted potential VPP lowers below reference potential VR. Ring oscillator
51
issues a clock signal PCLK to charge pump circuit
52
when signal LOW is at the active level of “H”. When signal LOW is at the inactive level of “L”, ring oscillator
51
does not issue clock signal PCLK.
Charge pump circuit
52
includes, as shown in
FIG. 18
, a capacitor
58
and N-channel MOS transistors
59
and
60
provided corresponding to each power supply line PL. One of the electrodes of capacitor
58
receives clock signal PCLK from ring oscillator
51
, and the other electrode is connected to a node N
58
. The gate and drain of N-channel MOS transistor
59
are connected to the line bearing power supply potential VCC, and the source thereof is connected to node N
58
. The gate and drain of N-channel MOS transistor
60
are connected to node N
58
, and the source thereof is connected to one end of corresponding power supply line PL. Each of N-channel MOS transistors
59
and
60
forms a diode.
While clock signal PCLK is at “L” level, a current flows from the line bearing power supply potential VCC to node N
58
through N-channel MOS transistor
59
so that node N
58
is charged to a potential of (VCC—Vth), where Vth is a threshold voltage of the N-channel MOS transistor. When clock signal PCLK subsequently rises from “L” level (ground potential GND) to “H” level (power supply potential VCC), the potential on node N
58
rises to (2VCC—Vth) as a result of coupling of capacitor
58
. Thereby, N-channe
Fujii Nobuyuki
Morishita Fukashi
Okamoto Mako
Taito Yasuhiko
Yamazaki Akira
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Potter Roy
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