Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-04-13
2002-05-28
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S533000, C257S534000, C257S535000
Reexamination Certificate
active
06396123
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a decoupling condenser.
2. Description of the Background Art
As one way to miniaturize semiconductor devices, a technique called “chemical mechanical polishing”(hereinafter, referred to as “CMP”) has conventionally been employed. In the CMP process, a surface of an interlayer insulating film or the like on a semiconductor substrate is polished for planarization to improve precision in photolithography in a subsequent process. This technique, however, has the following disadvantages. The surface of the interlayer insulating film may be polished excessively over an area where pattern density of gate electrodes or the like within the semiconductor chip is sparse, whereas it may be polished unsatisfactorily over an area with high pattern density. This creates an asperity on the surface of the interlayer insulating film. To prevent such an asperity, the variation in the pattern density of gate electrodes or the like to be formed on the semiconductor substrate should be reduced. To this effect, the area with sparse pattern density has been provided with dummy patterns, e.g., dummy gate electrodes, that are unnecessary for a circuit operation.
A structure of a semiconductor device having dummy patterns for use in the conventional CMP process will now be described with reference to
FIGS. 16
to
19
. As shown in
FIGS. 17 and 19
, a p
−
well
123
and an n
−
well
119
are formed below a main surface of a semiconductor substrate with a prescribed depth. In respective regions of p
−
well
123
and n
−
well
119
, as shown in
FIGS. 16 and 18
, element forming regions are formed, separated from one another by an isolating insulating film
135
. P
+
and n
+
impurity regions are formed in the element forming regions.
The p
+
and n
+
impurity regions in p
−
well
123
and n
−
well
119
are connected with contact plugs
140
and
145
, respectively. Contact plugs
140
are connected with a ground electrode (GND) interconnection line
114
, and thus, p
−
well
123
has a potential fixed by the ground electrode. Contact plugs
145
are connected with a power supply electrode (Vcc) interconnection line
113
, whereby n
−
well
119
has a potential fixed by the power supply electrode. In prescribed regions where the surfaces of p
−
well
123
and n
−
well
119
are exposed, gate insulating film dummy patterns
121
a
and
129
a
are formed, respectively, in the same layer as gate insulating films
121
and
129
. Gate electrode dummy patterns
131
a
and
139
a
are formed in the same layer as gate electrodes
131
and
139
.
In the semiconductor device having dummy patterns formed for use in the above-described conventional CMP process, gate electrode dummy patterns
131
a
and
139
a
formed in the gate electrode forming process are stacked on top of gate insulating film dummy patterns
121
a
and
129
a
formed in the gate insulating film forming process, respectively, as shown in
FIGS. 16 and 17
. Here, the gate electrode dummy patterns, which are floating conductive layers, induce parasitic capacitance, for which no countermeasures are taken. To lessen the adverse effects that such uncontrolled parasitic capacitance because of the floating conductive layers would pose on the electronic circuit, gate electrode dummy patterns
131
a
,
139
a
are disposed on isolating insulating film
135
in some cases, as shown in
FIGS. 18 and 19
.
FIG. 20
is a general equivalent circuit diagram of the conventional semiconductor device as described above. As shown in
FIG. 20
, the conventional semiconductor device has a circuit configuration in which elements are successively connected as follows. An external power supply electrode (Vcc) interconnection line
101
is connected to a power supply electrode (Vcc) pin
102
. Power supply electrode (Vcc) pin
102
is connected to a power supply electrode (Vcc) pad
103
. An external ground electrode (GND) interconnection line
104
is connected to a ground electrode (GND) pin
105
. Ground electrode (GND) pin
105
is connected to a ground electrode (GND) pad
106
. Electronic circuits
108
are connected in parallel with each other between power supply electrode (Vcc) pad
103
and ground electrode (GND) pad
106
.
A parasitic inductance
120
of power supplying lead frame is formed between external power supply electrode (Vcc) interconnection line
101
and power supply electrode (Vcc) pin
102
, and also between external ground electrode (GND) interconnection line
104
and ground electrode (GND) pin
105
. A parasitic inductance
130
of bonding wire is formed between power supply electrode (Vcc) pin
102
and power supply electrode (Vcc) pad
103
and also between ground electrode (GND) pin
105
and ground electrode (GND) pad
106
. Parasitic resistances
107
are formed on interconnection lines connecting power supply electrode (Vcc) pad
103
and electronic circuits
108
, and on interconnection lines connecting ground electrode (GND) pad
106
and electronic circuits
108
.
In the conventional semiconductor device as described above, electric fields are generated in parasitic inductance
120
of the lead frame and in parasitic inductance
130
of the bonding wire, in a direction to prevent an abrupt change of current. Therefore, there occur a drop of the potential of power supply electrode (Vcc) pad
103
, and an increase of the potential of ground electrode (GND) pad
106
, as expressed by the following equation (1).
&Dgr;
V×L=dI/dt
(1)
wherein &Dgr;V is a potential difference;
L is an inductance;
I is a current; and
t is a time.
There also occur local potential drop and increase within the semiconductor chip due to the parasitic resistance, as expressed by the following equation (2).
&Dgr;
V=I×R
(2)
wherein &Dgr;V is a potential difference;
I is a current; and
R is a resistance.
The operating voltage of the semiconductor device should be set taking into consideration the potential drop in power supply electrode (Vcc) pad
103
and the potential increase in ground electrode (GND) pad
106
as described above. This hinders reduction of the operating voltage of the semiconductor device.
Furthermore, noise is generated due to the abrupt change in the current flowing from one circuit to another circuit via the power supplying lead frame and the bonding wire, as expressed by equation (1). This causes electromagnetic waves to be emitted outwards from the semiconductor device. Such electromagnetic waves induce electromagnetic interference (EMI) in neighboring components of the semiconductor device.
One way of suppressing the local potential drop and increase within the circuits as well as the EMI between the semiconductor device and its neighboring components as described above is to provide the semiconductor device with a decoupling condenser. Providing a region dedicated to the decoupling condenser, however, will lead to an increase in an area required for the semiconductor device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device operable under a low voltage with suppressed EMI, by utilizing dummy patterns used in the above-described CMP process, without increasing the area occupied by the semiconductor device.
The semiconductor device according to the present invention is a semiconductor device having an electronic circuit and a decoupling condenser provided in parallel with each other between a power supply electrode and a ground electrode, wherein the electronic circuit includes a transistor. The decoupling condenser includes: an impurity region formed below a main surface of a semiconductor substrate with a prescribed depth; a dummy gate insulating film located on the impurity region, formed in the same layer as a gate insulating film of the transistor; and a dummy gate electrode located on the dummy gate insulating film, formed in the same l
Dickey Thomas L.
Tran Minh Loan
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