Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
2001-10-12
2004-08-10
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
C327S311000, C333S172000
Reexamination Certificate
active
06774714
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. P2000-313892, filed on Oct. 13, 2000; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device using a standard cell. Alternatively, the present invention relates to a semiconductor device provided with a noise cut filter for an Electromagnetic Susceptibility (EMS) countermeasure.
2. Description of the Related Art
There have been cases where malfunction occurs in semiconductor device such as a LSI or the like owing to external invasion of EMS. Therefore, in order to prevent malfunction, a countermeasure of EMS is provided to semiconductor device such as an LSI or the like. The EMS denotes a malfunction occurring in a cell C such as a buffer
11
owing to disturbance noise, which invaded from the input pad A of the LSI. As shown in
FIG. 1
, according to an EMS countermeasure of the LSI, a noise cut filter B is connected between pad A and cell C. The noise cut filter B has a resistance R
11
and a capacitor C
11
, which are connected in series.
In the case that a filter B for an EMS countermeasure is arranged and wired in a specific cell, the architecture of cell base LSI using a conventional cell is as follows.
As shown in
FIG. 1
, logic cells
100
to
108
and a logic cell C are aligned in the cell base architecture area by automatic arrangement and automatic wiring and wires
65
,
66
and
67
are wired in the logic cells
100
to
108
and the logic cell C. Next, an architect himself or herself searches for a specific cell C to be provided with the EMS countermeasure and the architect manually arranges and wires a filter B as an EMS countermeasure in an empty space in the metal signal wiring areas
41
,
43
and
45
. Alternatively, VDD power supply wires VDD
1
, VDD
2
and VSS power supply wires VSS
1
, VSS
2
are disposed between the cells
100
to
108
and between the signal wiring areas
41
,
43
and
45
. Wiring areas
42
,
44
and
46
have the signal wiring areas
41
,
43
and
45
, the VDD power supply wires VDD
1
, VDD
2
and the VSS power supply wires VSS
1
, VSS
2
. Thus, according to an earlier architecture method, manual work operation by the architect is inevitable, and the architecture and operating efficiency is very low.
SUMMARY OF THE INVENTION
A semiconductor integrated circuit according to embodiments of the present invention includes a first power supply wire capable of being set in a first electric potential, a second power supply wire capable of being set in a second electric potential, which is different from the foregoing first electric potential, a functional circuit, which is disposed between the foregoing first power supply wire and the foregoing second power supply wire, is connected to the foregoing first power supply wire or the foregoing second power supply wire and has a terminal, capable of inputting or outputting a signal with respect to the outside of the foregoing semiconductor integrated circuit, and a first capacitor disposed between the foregoing first power supply wire and the foregoing second power supply wire and one end of which is connected to the foregoing terminal.
A manufacturing method of a semiconductor device according to embodiments of the present invention includes a deciding a specification of the semiconductor device; a describing the decided specification in a logical expression; a forming a network list having a cell where an EMS countermeasure circuit is incorporated on the basis of the logical expression; a forming a layout pattern of the semiconductor device on the basis of the network list; and a processing a semiconductor substrate on the basis of the formed layout pattern to manufacture the semiconductor device.
REFERENCES:
patent: 5055669 (1991-10-01), Blake et al.
patent: 5324999 (1994-06-01), Hunley et al.
patent: 6043724 (2000-03-01), Frech et al.
patent: 6340913 (2002-01-01), Grundy
patent: 6657484 (2003-12-01), Bosshart
patent: 9-45855 (1997-02-01), None
Chida Tsuyoshi
Hegi Yasuhiro
Kabushiki Kaisha Toshiba
Le Dinh T.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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