Semiconductor device provided with conductive layer and...

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material

Reexamination Certificate

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C257S072000, C257S347000, C257S350000, C349S038000

Reexamination Certificate

active

06396077

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, liquid crystal displays, and manufacturing methods thereof. More specifically, it relates to a semiconductor device provided with a thin-film field effect transistor and a conductive layer, a liquid crystal display, and manufacturing methods thereof
2. Description of the Background Art
Conventionally, one type of liquid crystal display is known utilizing a thin-film field effect transistor formed with low-temperature polysilicon. Such a liquid crystal display usually requires a capacitor for accumulation of electric charges.
FIG. 13
shows a substrate with a thin-film field effect transistor of the liquid crystal display.
FIG. 13
is a schematic cross a sectional view showing a conventional liquid crystal display. Referring to
FIG. 13
, the conventional liquid crystal display will be described.
In
FIG. 13
, the liquid crystal display has a driver circuit region and a display pixel region. On a glass substrate
101
, a p channel thin-film field effect transistor
117
is located in the driver circuit region, whereas an n channel thin-film field effect transistor
118
and a storage capacitor
119
are located in the display pixel region.
In the driver circuit region, a base film
102
is formed on the glass substrate. Formed on base film
102
are source/drain regions
106
a,
106
b
and a channel region
107
of p type thin-film field effect transistor
117
, which are originally formed in the same layer of a polysilicon film as a semiconductor film. P type conductivity impurities are implanted into source/drain regions
106
a,
106
b.
An insulating film
108
serving as a gate insulating film is formed on source/drain regions
106
a,
106
b
and channel region
107
. In the region above channel region
107
, a gate electrode
109
a
is formed on insulating film
108
. A protective film
111
is formed on gate electrode
109
. Contact holes
112
a,
112
b
are formed opposite source/drain regions
106
a,
106
b
by partially etching protective film
111
and insulative film
108
. Electrodes
113
a,
113
b
are formed in contact holes
112
a,
112
b,
extending on the surface of protective film
111
. An insulative film
114
is formed on electrodes
113
a,
113
b
and protective film
111
.
In the display pixel region of the liquid crystal display, base film
102
is formed on glass substrate
101
. Formed on base film
102
are source/drain regions
104
a,
104
b
and a channel region
105
of an n channel thin-film field effect transistor
118
, which are originally formed in the same layer of a polysilicon film as a semiconductor film. In addition, on base film
102
, a lower electrode
103
of storage capacitor
119
is formed by the same layer of semiconductor film as that of source/drain regions
104
a,
104
b
and channel region
105
. Insulative film
108
is formed on source/drain regions
104
a,
104
b,
channel region
105
, and lower electrode
103
. Insulative film
108
has portions respectively serving as a gate insulating film of n channel thin-film field effect transistor
118
and a dielectric film of storage capacitor
119
. Namely, insulative film
108
on channel region
105
serves as a gate insulative film, whereas insulative film
108
on lower electrode
103
serves as a dielectric film. In the region on channel region
105
, a gate electrode
109
b
is formed on insulative film
108
. In the region on lower electrode
103
, a common electrode
110
is formed on insulative film
108
serving as a dielectric film. A protective film
111
is formed on gate electrode
109
b
and common electrode
110
. Protective film
111
and insulative mm
108
are partially etched and removed to form contact holes
112
c
to
112
e.
Electrodes
113
c
to
113
e
are respectively formed in contact holes
112
c
to
112
e
to extend on the surface of protective film
111
. An insulative film
114
is formed on electrodes
113
c
to
113
e
and protective film
111
. Thereafter, a transparent electrode and the like are formed in the display pixel region to manufacture a liquid crystal display in a conventional process.
As described above, the gate insulative film of p and n channel thin-film field effect transistors
117
and
118
and the dielectric film of storage capacitor
119
are formed by the same layer, i.e., insulative film
108
. Thus, the manufacturing process of the liquid crystal display is simplified
When a coplanar thin-film field effect transistor is used, lower electrode
103
of storage capacitor
119
is formed by implanting impurities in the same semiconductor film as that forming channel regions
107
and
105
of p and n channel thin-film field effect transistors
117
and
118
. This is because the thin-film field effect transistor is extremely sensitive to metal impurities in a process up to formation of the gate insulative film and it is substantially difficult to form a metal electrode below the gate insulative film.
FIGS. 14
to
16
are schematic cross sectional views shown in conjunction with the manufacturing method of the liquid crystal display in FIG.
13
. Referring to
FIGS. 14
to
16
, the manufacturing method of the liquid crystal display will be described.
Referring first to
FIG. 14
, a base film
102
is formed on a glass substrate
101
by a general method such as PECVD (Plasma Enhanced Chemical Vapor Deposition). A 2-layer film of silicon nitride and oxide films can be used as base film
102
. An amorphous silicon film is formed on base film
102
. The amorphous silicon film to be channel regions of p and n type thin-film field effect transistors
117
and
118
are annealed by an excimer laser to form a polysilicon film. Thereafter, a resist film is formed on the thus-formed polysilicon film. Polysilicon films
124
a
to
124
c
are formed as semiconductor films shown in
FIG. 14
by using the resist film as a mask for dry etching. Then, the resist film is removed.
Successively, phosphorus (P) ions, n type conductivity impurities are implanted in polysilicon film
124
c
to be a lower electrode of storage capacitor
119
. The phosphorus ions are selectively implanted in polysilicon film
124
c,
so that a resist film
125
is formed to cover polysilicon films
124
a
and
124
b
in a region excluding polysilicon film
124
c.
Phosphorus ions
129
are implanted in polysilicon film
124
c
by using resist film
125
as a mask to form a lower electrode
103
. The implantation of phosphorus ions
129
forms on resist film
125
a layer
126
of which a property has been changed by the implantation of phosphorus ions (hereinafter referred to as a changed layer
126
). On the other hand, the layer underlying resist film
125
has not been affected by the implantation of phosphorus ions
129
. Thus, resist film
125
includes two layers, changed layer
126
and unchanged layer
127
.
Thereafter, resist film
125
is removed. Note that if a usual stripper is used to remove changed layer
126
, the removal requires a considerable time or a changed layer
126
cannot be removed. Thus, plasma ashing with an oxygen plasma is used for the removal of changed layer
126
. More specifically, changed layer
126
is removed by directing oxygen plasma
133
to the surface of changed layer
126
of resist film
125
, as shown in FIG.
16
. After changed layer
126
is removed, a usual stripper is used to remove unchanged layer
127
.
Subsequently, insulative film
108
(see
FIG. 13
) serving as a gate insulative film and a dielectric film of storage capacitor
119
is formed. For example, a silicon oxide film formed by TEOS PECVD may be used as insulative film
108
. A chrome film is formed on insulative film
108
by sputtering. A resist film is formed on the chrome film. The chrome film is partially removed by etching using the resist film as a mask, so that gate electrodes
109
a,
109
b
and common electrode
110
(see
FIG. 13
) are formed. Storage capacitor
119
is formed by common electrode
110
, lower electrode
103
, an

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