Semiconductor device protection circuit

Electricity: electrical systems and devices – Safety and protection of systems and devices – Voltage regulator protective circuits

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Details

361 79, 361 86, 361103, 323276, 323281, 323285, 323901, H02H 902, H02H 710

Patent

active

049376977

ABSTRACT:
Semiconductor device protection circuit (10) provides increased power dissipation (current) limits for FET (11) when lower FET temperatures exist. The FET drain to source voltage (V.sub.DS) is monitored to provide a current sense signal (54). When the current sense signal exceeds a predetermined reference limit signal (V.sub.REF,55), a control circuit (23, 32) reduces current (power dissipation) in the FET. Circuitry (24) provides the reference limit signal (V.sub.REF) with a predetermined temperature variation as a function of the sensed temperature of the FET whereby for low device temperatures higher power dissipation (current) limits for the FET are provided. An additional control circuit (21, 30) provides short circuit overcurrent protection by reducing current in the FET when sensed FET current exceeds a predetermined limit. A delay circuit (39) inhibits operation of at least the control circuit (20, 32) until a predetermined time (t.sub.1) after the FET is turned on.

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patent: 4771357 (1988-09-01), Lorinez et al.
patent: 4787007 (1988-11-01), Matsumura et al.
patent: 4896245 (1990-01-01), Qualich

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