Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-10-15
2003-10-28
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S763000, C438S787000, C438S788000, C438S780000
Reexamination Certificate
active
06638873
ABSTRACT:
BACKGROUND OF THE INVENTION
This application claims the benefit of a Japanese Patent Application No. 2001-317666 filed Oct. 16, 2001, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to semiconductor device producing methods, and more particularly to a semiconductor device producing method which is characterized by a pre-processing for preventing a variation in an etching rate when selectively etching a barrier metal underlayer such as a wiring layer.
2. Description of the Related Art
Recently, due to increased integration density of semiconductor devices, there are demands to further increase the accuracy of patterns. In order to satisfy such demands, it is necessary to realize a dry etching technique which can accurately and stable etch the patterns.
A description will be given of an example of a conventional wiring layer forming process, by referring to
FIGS. 1 through 4
.
FIGS. 1 through 4
are cross sectional views for explaining this example of the conventional wiring layer forming process. For the sake of convenience, it is assumed that the etching process is carried out with respect to a TiW barrier metal layer using an induced combination plasma (ICP) etching apparatus.
First, as shown in
FIG. 1
, an i-type (intrinsic) AlGaAs buffer layer (not shown) is formed on a semiinsulating GaAs substrate (not shown). On this i-type AlGaAs buffer layer, an i-type InGaAs electron transit layer (not shown), an n-type AlGaAs electron supply layer
61
and an n-type GaAs cap layer
62
are successively grown epitaxially. A source/drain electrode
63
made up of a AuGe layer
64
and a Au layer
65
is formed on the n-type GaAs cap layer
62
. Then, after forming a gate recess region, a T-shaped gate electrode
66
made up of a Pt layer
67
and a Au layer
68
is formed on the n-type AlGaAs electron supply layer
61
. A polyimide layer
69
covers the entire surface of this structure, as an interlayer insulation layer.
Next, an ICP etching is carried out to selectively etch the polyimide layer
69
, so as to form a contact hole
70
which reaches the source/drain electrode
63
. Thereafter, a TiW layer
71
which forms a barrier metal and a Au seed layer
72
which forms a plating seed are successively sputtered.
Further, an electroplating is carried out by using a resist pattern
73
as a plating frame, so as to selectively form a Au wiring layer
74
.
Next, as shown in
FIG. 2
, an ion milling apparatus is used to remove by an Ar ion milling the Au seed layer
72
which is exposed at a region where the Au wiring layer
74
is not provided.
Then, after cleaning the ICP etching apparatus, the ICP etching apparatus is run using a dummy wafer
88
provided with a TiW layer
89
which becomes an etching target, in FIG.
3
.
The ICP etching apparatus includes an etching reaction chamber
81
which is provided with a quartz plate
82
for supporting a planar coil
83
and a quartz window
84
which forms an observation port. A stage
85
, which is also functions as an electrode on which the sample is placed, is accommodated within the etching reaction chamber
81
.
The etching reaction chamber
81
is grounded, and a high-frequency power for plasma excitation is applied to the planar coil
83
from an excitation RF power supply
87
. On the other hand, a bias power from a bias RF power supply
86
is applied to the stage
85
.
During this running process, the dummy wafer
88
used is provided with the TiW layer
89
which is the same as the etching target of the etching process, and the TiW layer
89
is etched by introducing a SF
6
gas into the etching reaction chamber
81
and generating plasma
90
by the excitation RF power supply
87
.
Next, the dummy wafer
88
is removed from the etching reaction chamber
81
in
FIG. 3
, and the semiconductor wafer having the exposed portion of the TiW layer
71
is placed on the stage
85
. Then, a SF
6
gas is introduced into the etching reaction chamber
81
and the plasma
90
is generated by the excitation RF power supply
87
. Hence, the exposed TiW layer
71
is selectively etched by the generated plasma, so as to separate the Au wiring layer
74
into portions which are electrically isolated from each other as shown in FIG.
4
.
However, when the etching of the TiW barrier metal is carried out a number of times on this ICP etching apparatus, there is a problem in that the etching rate initially varies suddenly, thereby making it difficult to realize a stable etching. This problem will now be described by referring to
FIGS. 5 and 6
.
FIG. 5
is a diagram for explaining a dependency of the etching rate on a number of times of the etching carried out when the etching of the TiW barrier metal shown in
FIG. 4
is repeated. In
FIG. 5
, the ordinate indicates the etching rate (nm/min), and the abscissa indicates the number of etchings (time), that is, the number of times of the etching carried out.
It may be seen from
FIG. 5
that the etching rate initially varies suddenly, but thereafter enters a stable region.
FIG. 5
shows a case where the etching is carried out for 1 minute for each time of the etching carried out. In
FIG. 5
, it may be seen that the etching rate after
10
etchings is approximately ½ the initial etching rate.
FIG. 6
is a diagram for explaining a dependency of the etching rate on a number of times of the etching carried out when the etching of only the TiW barrier metal which does not involve exposure of the Au layer is repeated. In
FIG. 6
, the ordinate indicates the etching rate (nm/min), and the abscissa indicates the number of etching times (times), that is, the number of times of the etching carried out.
It may be seen from
FIG. 6
that the etching rate dot not vary suddenly.
From a comparison of
FIGS. 5 and 6
, it may be regarded that the sudden variation in the initial etching rate is caused due to the Au wiring layer
74
and the Au seed layer
72
which are exposed during the etching process carried out with respect to the TiW layer
71
. In other words, since the Au wiring layer
74
and the Au seed layer
72
are exposed during the etching process carried out with respect to the TiW layer
71
, it may be regarded that the exposed portion of Au scatters into the etching reaction chamber
81
to cause deterioration of the etching rate.
The tendency of the etching rate varying suddenly when the Au is exposed can similarly be observed for other metals which are exposed, such as Pt, Cu and Al.
The above described process of forming the wiring layer uses the selective plating. However, the sudden variation of the etching rate similarly occurs when the entire wiring layer is formed by sputtering or the like and an etching is carried out using a resist pattern as a mask to form the wiring pattern. In this case, a side edge portion of the Au wiring layer immediately under the resist pattern is exposed at the etching portion, and thus, it may be regarded that the Au scatters into the etching reaction chamber from this exposed side edge portion to thereby cause the sudden variation in the etching rate.
The sudden variation of the etching rate described above is not limited to the etching process with respect to the barrier metal. As will be described in conjunction with
FIGS. 7 and 8
, the sudden variation of the etching rate also occurs during the process of forming the contact hole in the interlayer insulation layer such as the polyimide layer
69
shown in FIG.
1
.
FIG. 7
is a diagram for explaining a dependency of the etching rate on a number of times of the etching carried out when the process of forming the contact hole in
FIG. 1
is repeated. In
FIG. 7
, the ordinate indicates the etching rate (nm/min), and the abscissa indicates the number of etchings (time), that is, the number of times of the etching carried out.
It may be seen from
FIG. 7
that the etching rate initially varies suddenly, but thereafter enters a stable region.
FIG. 7
shows a case where the etching is carried out
Fujitsu Quantum Devices Limited
Lebentritt Michael S.
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