Chemistry: electrical and wave energy – Apparatus – Electrolytic
Reexamination Certificate
1999-12-02
2002-11-12
Nguyen, Nam (Department: 1741)
Chemistry: electrical and wave energy
Apparatus
Electrolytic
C204S267000, C204S269000, C204S22400M, C118S044000
Reexamination Certificate
active
06478935
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
This invention relates to a method for manufacturing a semiconductor device comprising forming elements such as damascene interconnects and an interlayer connecting hole by a plating technique; and a plating apparatus and a sputtering apparatus therefor.
2. Description of the related art
A sputtering or CVD technique has been commonly used as a metal-film deposition procedure for forming interconnects and an inter-layer connecting hole in a semiconductor device. These techniques, however, require a considerable cost and a complicated process because a great deal of energy is applied to a metal compound to liberate or separate the metal from the corresponding metal compound for depositing the metal on a surface where a semiconductor device will be formed. Furthermore, sputtering may not provide adequate coverage. To solve these problems, electroplating for depositing a metal film has recently received attention.
A conventional manufacturing process for a semiconductor device will be described with reference to
FIG. 5
in terms of forming damascene copper interconnects.
An insulating film
2
is deposited on a silicon substrate
1
and then a groove
5
is formed in a given area. Then, on the overall surface is deposited by sputtering a barrier-metal film
3
consisting of TiN e.g., 20 nm of thickness. Then, on the surface is deposited by sputtering a seed-metal film
4
consisting of copper for growing copper plating (FIG.
5
(
a
)). The sputtering conditions are, for example, as follows; a substrate temperature: 0° C., a sputter power: 2 kW, a pressure: 2 mTorr, and a distance between a target and the substrate: 60 mm.
Then, the substrate is subject to plating by immersing it in an aqueous solution of cupric sulfate at an ambient temperature.
The plated substrate is left at an ambient temperature to stabilize the structure of the copper (FIG.
5
(
b
)). The treatment is hereinafter referred to as “self-annealing”. Duration for the self-annealing is generally about 50 to 80 hours.
Then, the substrate surface is smoothed by chemical mechanical polishing (CMP) to form damascene copper interconnects.
The prior art has the following problems.
First, a void may be generated inside the groove or the hole due to shrinkage of the copper plating during the self-annealing step. A copper plating has a sparse structure immediately after plating. After self-annealing the copper structure gradually comes to be thermodynamically stable as grains grow. In the course of the process, copper shrinks to generate a void inside the groove as shown in FIG.
5
(
b
).
Second, small grains in a seed-metal film deposited for forming a plating layer remain after the self-annealing, leading to a less reliable device.
SUMMARY OF THE INVENTION
To solve the above problems, an object of this invention is to prevent void generation inside a groove or hole during forming damascene interconnects or an inter-layer connecting hole. Another object of this invention is to eliminate residual small grains in a seed-metal film for improving reliability of a device.
This invention provides a method for manufacturing a semiconductor device comprising the steps of:
forming an insulating film on a semiconductor substrate and then forming a groove or hole in a given area of the insulating film;
forming a barrier-metal film filling the groove or hole;
forming a seed-metal film on the barrier-metal film formed inside the groove or hole; and
forming the first plating film on the seed-metal film using a metal material;
conducting the first annealing for a given period;
forming the second plating film consisting of the above metal material on the first plating film; and
conducting the second annealing for a given period.
Plating for forming damascene interconnects has been conventionally conducted in a single step in the light of various factors such as yield. On the other hand, according to this invention, a plating film is formed in two separate steps (hereinafter, referred to as a “divided plating” technique) to prevent void generation inside a groove or hole. Specifically, void generation can be avoided in a groove for forming damascene interconnects or a hole for forming an inter-layer connecting hole. In this invention, the first annealing is conducted after the first plating, i.e., the annealing is conducted when the plating film is thin. The absolute amount of the metal used in the plating process is therefore so small that its shrinkage is reduced and thus a frequency of void generation may be minimized. Even when a void is generated, the film thickness of the plating film is thin in the first annealing, i.e., the distance between the void and the plating surface is short, so that the void may easily disappear. As described above, void generation can be prevented inside the groove or hole.
In this invention, annealing may be self-annealing at an ambient temperature or hot-annealing at an elevated temperature, e.g., 300° C. or higher. Hot-annealing has an advantage of reduction in an annealing time. For example, an annealing time may be about 30 min at a heating temperature of 300° C.
In the method for manufacturing a semiconductor device, the thickness of the first plating film can be 0.1 to 0.5 folds of the width of the groove or hole.
This invention also provides a method for manufacturing a semiconductor device comprising the steps of:
forming an insulating film on a semiconductor substrate and then forming a groove or hole in a given area of the insulating film;
forming a barrier-metal film filling the groove or hole;
forming a seed-metal film on the barrier-metal film formed inside the groove or hole; and
forming a plating film on the seed-metal film using a metal material, and then conducting annealing for a given period; and
where the metal plating film is formed at a plating temperature of 65 to 100° C.
As described above, shrinkage of a plating metal film is effectively minimized for preventing void generation inside a groove or hole, which may be achieved by plating at a higher temperature of 65 to 100° C. in the method of this invention (hereinafter, referred to as a “hot plating” technique). A metal plating film for forming damascene interconnects has been commonly formed at a relatively lower temperature from an ambient temperature to 60° C. Especially, using copper, the process is generally conducted at an ambient temperature. On the other hand, we have found that when plating is conducted at a higher temperature of 65° C. or higher, grains grow substantially simultaneously with deposition, which can significantly reduce shrinkage of the plating metal film after deposition, prevent void generation and reduce an annealing time. The effects are particularly remarkable at a temperature of 65° C. or higher, and more remarkable at 80° C. or higher although a temperature of 100° C. or higher may be undesirable due to foaming during the plating process.
This invention also provides a method for manufacturing a semiconductor device comprising the steps of:
forming an insulating film on a semiconductor substrate and then forming a groove or hole in a given area of the insulating film;
forming a barrier-metal film filling the groove or hole;
forming a seed-metal film on the barrier-metal film formed inside the groove or hole;
forming a plating film on the seed-metal film using a metal material while distorting the semiconductor substrate into a concave where the center of the surface to be plated extrudes; and
conducting annealing for a given period.
In a conventional plating process, a residual tensile stress is generated when a metal material which may initiate self-annealing is used. Such a residual stress is probably generated due to shrinkage of a plating film in association with increase of the grain size of the plating metal during the self-annealing process after forming the plating film.
In other words, a tensile stress in a plating film may act in a direction interfering with shrinkage of the plating film, resulting in inhibiting self-annealing associa
NEC Corporation
Nguyen Nam
Nicolas Wesley A.
Young & Thompson
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